CC is measured with all output pins disconnected; XTAL1 dr" />
參數(shù)資料
型號: DSPIC33FJ32GP202T-I/SO
廠商: Microchip Technology
文件頁數(shù): 64/176頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 32K 28SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,600
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
其它名稱: DSPIC33FJ32GP202T-I/SOTR
154
AT89C5131
4136C–USB–04/05
Notes:
1. Operating I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 73.), VIL =
V
SS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
70.).
2. Idle I
CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = V
CC; EA = RST = VSS (see Figure 71).
3. Power-down I
CC is measured with all output pins disconnected; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 72.). In addition, the WDT must be inactive and the POF flag must be set.
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OLS of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed
0.45V with maxi V
OL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.
6. Under steady state (non-transient) conditions, I
OL must be externally limited as follows:
Maximum I
OL per port pin: 10 mA
Maximum I
OL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I
OL for all output pins: 71 mA
If I
OL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
Figure 70. I
CC Test Condition, Active Mode
V
PFDM
Power Fail Low Level Threshold
2.2
V
Power fail hysteresis V
PFDP - VPFDM
0.15
V
Symbol
Parameter
Min
Typ
(5)
Max
Unit
Test Conditions
EA
V
CC
VCC
I
CC
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
VCC
P0
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