參數(shù)資料
型號(hào)： DT28F016SV-080
廠商： INTEL CORP
元件分類： DRAM
英文描述： 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
中文描述： 1M X 16 FLASH 5V PROM, 80 ns, PDSO56
封裝： 23.70 X 16 MM, SSOP-56
文件頁數(shù)： 11/63頁
文件大?。?/td> 635K
代理商： DT28F016SV-080
E
2.1 Lead Descriptions
28F016SV FlashFile MEMORY
11
Symbol
Type
Name and Function
A
0
INPUT
BYTE-SELECT ADDRESS:
Selects between high and low byte when
device is in x8 mode. This address is latched in x8 data programs. Not
used in x16 mode (i.e., the A
0
input buffer is turned off when BYTE# is
high).
WORD-SELECT ADDRESSES:
Select a word within one 64-Kbyte block.
A
6
–15
selects 1 of 1024 rows, and A
1
–5
selects 16 of 512 columns. These
addresses are latched during data programs.
BLOCK-SELECT ADDRESSES:
Select 1 of 32 Erase blocks. These
addresses are latched during data programs, erase and lock block
operations.
LOW-BYTE DATA BUS:
Inputs data and commands during CUI program
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
HIGH-BYTE DATA BUS:
Inputs data during x16 data program
operations. Outputs array, buffer or identifier data in the appropriate read
mode; not used for Status Register reads. Floated when the chip is de-
selected or the outputs are disabled.
CHIP ENABLE INPUTS
: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE
0
# or CE
1
# high, the device
is de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE
0
#
and CE
1
# must be low to select the device.
All timing specifications are the same for both signals. Device Selection
occurs with the latter falling edge of CE
0
# or CE
1
#. The first rising edge of
CE
0
# or CE
1
# disables the device.
RESET/POWER-DOWN:
RP# low places the device in a deep power-
down state. All circuits that consume static power, even those circuits
enabled in standby mode, are turned off. When returning from deep
power-down, a recovery time of t
PHQV
is required to allow these circuits to
power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
Exit from deep power-down places the device in read array mode.
OUTPUT ENABLE:
Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WRITE ENABLE:
Controls
access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
Page Buffer addresses are latched on the falling edge of WE#.
A
1
–A
15
INPUT
A
16
–A
20
INPUT
DQ
0
–DQ
7
INPUT/OUTPUT
DQ
8
–DQ
15
INPUT/OUTPUT
CE
0
#, CE
1
#
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
相關(guān)PDF資料
PDF描述
DT28F016SV-100 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
DT28F016SA-100 28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8)FlashFile MEMORY
DT28F016SA-150 28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8)FlashFile MEMORY
DT28F160F3B120 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160F3B95 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DT28F016SV-100 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile MEMORY
DT28F160 制造商:Intel 功能描述:
DT28F160F3B120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160F3B95 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
DT28F160F3T120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
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