參數(shù)資料
型號(hào)： DZPD6722VCCE
廠商： INTEL CORP
元件分類： 總線控制器
英文描述： ISA-to-PC-Card (PCMCIA) Controllers
中文描述： PCMCIA BUS CONTROLLER, PQFP208
封裝： LQFP-208
文件頁數(shù)： 62/138頁
文件大?。?/td> 723K
代理商： DZPD6722VCCE
PD6710/
’
22
—
ISA-to-PC-Card (PCMCIA) Controllers
62
Datasheet
8.6
Card I/O Map 0
–
1 Offset Address Low
There are two separate Card I/O Map Offset Address Low registers, each with identical fields.
These registers are located at the following indexes:
Index
36h
38h
Card I/O Map Offset Address Low
Card I/O Map 0 Offset Address Low
Card I/O Map 1 Offset Address Low
Bits 7:1
—
Offset Address 7:1
This register contains the least-significant byte of the quantity that will be added to the host I/O
address; this will determine the PC Card I/O map location where the I/O access will occur.
The most-significant byte is located in the
Card I/O Map 0
–
1 Offset Address High
register (see
“
Card I/O Map 0
–
1 Offset Address High
”
on page 62
).
8.7
Card I/O Map 0
–
1 Offset Address High
There are two separate Card I/O Map Offset Address High registers, each with identical fields.
These registers are located at the following indexes:
Index
37h
39h
Card I/O Map Offset Address High
Card I/O Map 0 Offset Address High
Card I/O Map 1 Offset Address High
Register Name:
Card I/O Map 0
–
1 Offset Address Low
Index:
36h, 38h
Register Per:
socket
Register Compatibility Type:
ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 7:1
0
1
RW:0000000
RW:0
1. This bit must be programmed to
‘
0
’
.
Register Name:
Card I/O Map 0
–
1 Offset Address High
Index:
37h, 39h
Register Per:
socket
Register Compatibility Type:
ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 15:8
RW:00000000
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