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參數(shù)資料
| 型號： | E28F160S5-70 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 2M X 8 FLASH 5V PROM, 70 ns, PDSO56 |
| 封裝： | 14 X 20 MM, TSOP-56 |
| 文件頁數(shù)： | 40/50頁 |
| 文件大?。?/td> | 1220K |
| 代理商： | E28F160S5-70 |
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28F160S5, 28F320S5
E
40
ADVANCE INFORMATION
6.2.1
CAPACITANCE
Table 18. Capacitance
(1)
, T
A
= +25°C, f = 1 MHz
Symbol
Parameter
Typ
Max
Unit
Condition
C
IN
Input Capacitance
6
8
pF
V
IN
= 0.0V
C
OUT
Output Capacitance
8
12
pF
V
OUT
= 0.0V
NOTE:
1.
Sampled, not 100% tested.
6.2.2
AC INPUT/OUTPUT TEST CONDITIONS
TEST POINTS
INPUT
OUTPUT
1.5
3.0
0.0
1.5
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for V
CC
= 5.0V ± 5%
(High Speed Testing Configuration)
TEST POINTS
INPUT
OUTPUT
2.0
0.8
0.8
2.0
2.4
0.45
AC test inputs are driven at V
(2.4 V
) for a Logic "1" and V
(0.45 V
) for a Logic "0." Input timing begins at V
IH
(2.0 V
TTL
) and V
IL
(0.8 V
TTL
). Output timing ends at V
IH
and V
IL
. Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for V
CC
= 5.0V ± 10%
(Standard Testing Configuration)
DEVICE
UNDER
TEST
1.3V
1N914
C
L
OUT
R = 3.3 k
C Includes Jig
Capacitance
Figure 15. Transient Equivalent Testing
Load Circuit
Test Configuration Capacitance Loading Value
Test Configuration
C
L
(pF)
V
CC
= 5.0V
±
5%
30
V
CC
= 5.0V
±
10%
100
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