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參數(shù)資料
| 型號： | E28F320J3A-110 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 3 Volt Intel StrataFlash⑩ Memory |
| 中文描述： | 2M X 16 FLASH 2.7V PROM, 110 ns, PDSO56 |
| 封裝： | 14 X 20 MM, TSOP-56 |
| 文件頁數(shù)： | 12/58頁 |
| 文件大?。?/td> | 380K |
| 代理商： | E28F320J3A-110 |
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28F128J3A, 28F640J3A, 28F320J3A
6
Preliminary
2.0
Principles of Operation
The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program,
and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power
supplies during block erasure, program, lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.
After initial device power-up or return from reset/power-down mode (see
Section 3.0,
“
Bus
Operations
”
on page 7
), the device defaults to read array mode. Manipulation of external memory
control pins allows array read, standby, and output disable operations.
Read array, status register, query, and identifier codes can be accessed through the CUI (Command
User Interface) independent of the V
PEN
voltage. V
PENH
on V
PEN
enables successful block
erasure, programming, and lock-bit configuration. All functions associated with altering memory
contents
—
block erase, program, lock-bit configuration
—
are accessed via the CUI and verified
through the status register.
Commands are written using standard micro-processor write timings. The CUI contents serve as
input to the WSM, which controls the block erase, program, and lock-bit configuration. The
internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and
margining of data. Addresses and data are internally latched during program cycles.
Interface software that initiates and polls progress of block erase, program, and lock-bit
configuration can be stored in any block. This code is copied to and executed from system RAM
during flash memory updates. After successful completion, reads are again possible via the Read
Array command. Block erase suspend allows system software to suspend a block erase to read or
program data from/to any other block. Program suspend allows system software to suspend a
program to read data from any other flash memory array location.
2.1
Data Protection
Depending on the application, the system designer may choose to make the V
PEN
switchable
(available only when memory block erases, programs, or lock-bit configurations are required) or
hardwired to V
PENH
. The device accommodates either design practice and encourages
optimization of the processor-memory interface.
When V
PEN
≤
V
PENLK
, memory contents cannot be altered. The CUI
’
s two-step block erase, byte/
word program, and lock-bit configuration command sequences provide protection from unwanted
operations even when V
PENH
is applied to V
PEN
. All program functions are disabled when V
CC
is
below the write lockout voltage V
LKO
or when RP# is V
IL
. The device
’
s block locking capability
provides additional protection from inadvertent code or data alteration by gating erase and program
operations.
相關PDF資料 |
PDF描述 |
|---|---|
| E28F320J3A-115 | Intel StrataFlash Memory (J3) |
| E28F320J3A-120 | Intel StrataFlash Memory (J3) |
| E28F320J3A-125 | Intel StrataFlash Memory (J3) |
| E28F320J3A-150 | Intel StrataFlash Memory (J3) |
| E28F320J3C-115 | Intel StrataFlash Memory (J3) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| E28F320J3A110SL5FS | 功能描述:IC FLASH 32MBIT 110NS 56TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應商設備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
| E28F320J3A-115 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
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