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參數(shù)資料
| 型號： | E28F320J3A-110 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | 3 Volt Intel StrataFlash⑩ Memory |
| 中文描述： | 2M X 16 FLASH 2.7V PROM, 110 ns, PDSO56 |
| 封裝： | 14 X 20 MM, TSOP-56 |
| 文件頁數(shù)： | 31/58頁 |
| 文件大?。?/td> | 380K |
| 代理商： | E28F320J3A-110 |
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28F128J3A, 28F640J3A, 28F320J3A
Preliminary
25
4.11.1
Read Configuration
The device will support both asynchronous page mode and standard word/byte reads. No
configuration is required.
Status register and identifier only support standard word/byte single read operations.
Table 18. Read Configuration Register Definition
4.12
Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once
the STS pin has been configured, it remains in that configuration until another configuration
command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation
where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state
machine is ready for a new operation or suspended.
Table 19,
“
Configuration Coding Definitions
”
on page 26
displays the possible STS configurations.
To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed
by the desired configuration code. The three alternate configurations are all pulse mode for use as a
system interrupt as described below. For these configurations, bit 0 controls Erase Complete
interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h
configuration code with the Configuration command resets the STS pin to the default RY/BY#
level mode. The possible configurations and their usage are described in
Table 19,
“
Configuration
Coding Definitions
”
on page 26
. The Configuration command may only be given when the device
is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in
both status register bits SR.4 and SR.5 being set to
“
1.
”
When configured in one of the pulse
modes, the STS pin pulses low with a typical pulse width of 250 ns.
RM
R
R
R
R
R
R
R
16 (A
16
)
15
14
13
12
11
10
9
R
R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
Notes
RCR.16 = READ MODE (RM)
0 = Standard Word/Byte Reads Enabled (Default)
1 = Page-Mode Reads Enabled
Read mode configuration effects reads from the flash array.
Status register, query, and identifier reads support standard
word/byte read cycles.
RCR.15
–
1 = RESERVED FOR FUTURE ENHANCEMENTS (R)
These bits are reserved for future use. Set these bits to
“
0.
”
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| E28F320J3A-115 | Intel StrataFlash Memory (J3) |
| E28F320J3A-120 | Intel StrataFlash Memory (J3) |
| E28F320J3A-125 | Intel StrataFlash Memory (J3) |
| E28F320J3A-150 | Intel StrataFlash Memory (J3) |
| E28F320J3C-115 | Intel StrataFlash Memory (J3) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| E28F320J3A110SL5FS | 功能描述:IC FLASH 32MBIT 110NS 56TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
| E28F320J3A-115 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| E28F320J3A-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
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