參數(shù)資料
型號(hào)： E28F320J3A-110
廠商： INTEL CORP
元件分類： PROM
英文描述： 3 Volt Intel StrataFlash⑩ Memory
中文描述： 2M X 16 FLASH 2.7V PROM, 110 ns, PDSO56
封裝： 14 X 20 MM, TSOP-56
文件頁(yè)數(shù)： 15/58頁(yè)
文件大?。?/td> 380K
代理商： E28F320J3A-110
28F128J3A, 28F640J3A, 28F320J3A
Preliminary
9
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel
Flash memories
allow proper initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.5
Read Query
The read query operation outputs block status information, CFI (Common Flash Interface) ID
string, system interface information, device geometry information, and Intel-specific extended
query information.
3.6
Read Identifier Codes
The read identifier codes operation outputs the manufacturer code, device code and the block lock
configuration codes for each block (see
Figure 5 on page 10
). Using the manufacturer and device
codes, the system CPU can automatically match the device with its proper algorithms. The block
lock configuration codes identify locked and unlocked blocks.
3.7
Write
Writing commands to the CUI enables reading of device data, query, identifier codes, inspection
and clearing of the status register, and, when V
PEN
= V
PENH
, block erasure, program, and lock-bit
configuration.
The Block Erase command requires appropriate command data and an address within the block to
be erased. The Byte/Word Program command requires the command and address of the location to
be written. Set Block Lock-Bit commands require the command and block within the device to be
locked. The Clear Block Lock-Bits command requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device is enabled
and WE# is active. The address and data needed to execute a command are latched on the rising
edge of WE# or the first edge of CE
0
, CE
1
, or CE
2
that disables the device (see
Table 2
). Standard
microprocessor write timings are used.
4.0
Command Definitions
When the V
PEN
voltage
≤
V
PENLK
, only read operations from the status register, query, identifier
codes, or blocks are enabled. Placing V
PENH
on V
PEN
additionally enables block erase, program,
and lock-bit configuration operations.
Device operations are selected by writing specific commands into the CUI.
Table 4
defines these
commands.
相關(guān)PDF資料
PDF描述
E28F320J3A-115 Intel StrataFlash Memory (J3)
E28F320J3A-120 Intel StrataFlash Memory (J3)
E28F320J3A-125 Intel StrataFlash Memory (J3)
E28F320J3A-150 Intel StrataFlash Memory (J3)
E28F320J3C-115 Intel StrataFlash Memory (J3)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
E28F320J3A110SL5FS 功能描述:IC FLASH 32MBIT 110NS 56TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁(yè)面:1445 (CN2011-ZH PDF)
E28F320J3A-115 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
E28F320J3A-120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
E28F320J3A-125 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
E28F320J3A-150 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3)
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