35
SAM4CP [DATASHEET]
43051E–ATPL–08/14
8.1.4.4 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several
consecutive pages, and each lock region has its associated lock bit.
The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.1.4.5 Security Bit Feature
The SAM4CP features a security bit based on a specific General Purpose NVM bit (GPNVM bit 0). When the security is
enabled, any access to the Flash, SRAM, Core Registers and Internal Peripherals, either through the SW-DP/JTAG-DP
interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code
programmed in the Flash.
This security bit can only be enabled through the command “Set General Purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals
are permitted.
8.1.4.6 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the
user. The ERASE pin has no effect on the unique identifier.
8.1.4.7 User Signature
The memory has one additional reprogrammable page that can be used as page signature by the user. It is accessible
through specific modes, for erase, write and read operations. Erase pin assertion will not erase the User Signature page.
8.1.4.8 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through
a multiplexed fully-handshaked parallel port. It allows gang programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
8.1.4.9 SAM-BA Boot
The SAM-BA Boot is a default Boot Program for the master processor (CM4P0) which provides an easy way to program
in-situ the on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART0.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
8.1.4.10GPNVM Bits
The SAM4CP features two GPNVM bits. These bits can be cleared or set respectively through the commands “Clear
GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
Table 8-1.
Lock bit number
Product
Number of Lock Bits
Lock Region Size
SAM4CP16B
128
8 Kbytes
Table 8-2.
General-purpose Nonvolatile Memory Bits
GPNVMBit[#]
Function
0
Security bit
1
Boot mode selection