654
SAM4CP [DATASHEET]
43051E–ATPL–08/14
33.7.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the Peripheral Clock, by a value between 1 and 255.
If the SCBR field in the SPI_CSR is programmed to 1, the operating baud rate is peripheral clock (see the “Electrical
Characteristics” section for the SPCK maximum frequency). Triggering a transfer while SCBR is at 0 can lead to
unpredictable results
.
At reset, SCBR is 0 and the user has to program it to a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field. This allows
the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.
33.7.3.4 Transfer Delays
Figure 33-9
shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be
programmed to modify the transfer waveforms:
Delay between the chip selects - programmable only once for all chip selects by writing the DLYBCS field in the
SPI_MR. The SPI slave device deactivation delay is managed through DLYBCS. If there is only one SPI slave
device connected to the master, the DLYBCS field does not need to be configured. If several slave devices are
connected to a master, DLYBCS must be configured depending on the highest deactivation delay. Refer to the SPI
slave device electrical characteristics.
Delay before SPCK - independently programmable for each chip select by writing the DLYBS field. The SPI slave
device activation delay is managed through DLYBS. Refer to the SPI slave device electrical characteristics to
define DLYBS.
Delay between consecutive transfers - independently programmable for each chip select by writing the DLYBCT
field. The time required by the SPI slave device to process received data is managed through DLYBCT. This time
depends on the SPI slave system activity.
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
Figure 33-9.
Programmable Delays
33.7.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS
signals are high before and after each transfer.
Fixed Peripheral Select Mode
: SPI exchanges data with only one peripheral.
Fixed peripheral select mode is enabled by writing the PS bit to zero in the SPI_MR. In this case, the current
peripheral is defined by the PCS field in the SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select Mode:
Data can be exchanged with more than one peripheral without having to
reprogram the NPCS field in the SPI_MR.
Variable Peripheral Select mode is enabled by setting PS bit to 1 in the SPI_MR. The PCS field in the SPI_TDR is
used to select the current peripheral. This means that the peripheral selection can be defined for each new data.
The value to write in the SPI_TDR register as the following format.
DLYBCS
DLYBS
DLYBCT
DLYBCT
Chip Select 1
Chip Select 2
SPCK