180
SAM4CP [DATASHEET]
43051E–ATPL–08/14
12.7.2 Address Map
The address map of the
Private peripheral bus
(PPB) is given in the following table:
In register descriptions:
The
required privilege
gives the privilege level required to access the register, as follows:
Privileged: Only privileged software can access the register.
Unprivileged: Both unprivileged and privileged software can access the register.
12.8
Nested Vectored Interrupt Controller (NVIC)
This section describes the NVIC and the registers it uses. The NVIC supports:
1 to 41 interrupts.
A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is
the highest interrupt priority.
Level detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external
Non-maskable interrupt
(NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction overhead. This provides low latency exception handling.
12.8.1 Level-sensitive Interrupts
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral
deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripheral, causing it to clear the
interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see
“Hardware and
Software Control of Interrupts”
). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns
from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the
peripheral can hold the interrupt signal asserted until it no longer requires servicing.
12.8.1.1 Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
The NVIC detects that the interrupt signal is HIGH and the interrupt is not active.
The NVIC detects a rising edge on the interrupt signal.
A software writes to the corresponding interrupt set-pending register bit, see
“Interrupt Set-pending Registers”
, or
to the NVIC_STIR to make an interrupt pending, see
“Software Trigger Interrupt Register”
.
Table 12-29. Core Peripheral Register Regions
Address
Core Peripheral
0xE000E008 - 0xE000E00F
System Control Block
0xE000E010 - 0xE000E01F
System Timer
0xE000E100 - 0xE000E4EF
Nested Vectored Interrupt Controller
0xE000ED00 - 0xE000ED3F
System Control block
0xE000ED90 - 0xE000EDB8
Memory Protection Unit
0xE000EF00 - 0xE000EF03
Nested Vectored Interrupt Controller
0xE000EF30 - 0xE000EF44
Floating-point Unit