參數(shù)資料
型號: EDE2104ABSE-5C-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 2G bits DDR2 SDRAM
中文描述: 512M X 4 DDR DRAM, 0.5 ns, PBGA68
封裝: ROHS COMPLIANT, FBGA-68
文件頁數(shù): 55/81頁
文件大?。?/td> 604K
代理商: EDE2104ABSE-5C-E
EDE2104ABSE, EDE2108ABSE
Preliminary Data Sheet E1196E10 (Ver. 1.0)
55
Burst Read Command [READ]
The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start
of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency
(RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.
The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out
appears on the DQ pin in phase with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set
(MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set
(EMRS).
READ
NOP
/CK
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
DQS, /DQS
DQ
out0 out1 out2 out3
CL = 3
RL = 3
tDQSCK
Burst Read Operation (RL = 3, BL = 4 (AL = 0 and CL = 3))
READ
NOP
/CK
CK
T0
T1
T2
T3
T4
T5
T6
T7
T8
Command
DQS, /DQS
DQ
out0 out1 out2 out3 out4 out5 out6 out7
tDQSCK
CL = 3
RL = 3
Burst Read Operation (RL = 3, BL = 8 (AL = 0 and CL = 3))
相關(guān)PDF資料
PDF描述
EDE2104ABSE-6E-E 2G bits DDR2 SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDE2104ABSE-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM
EDE2104ABSE-8G-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM
EDE2108ABSE 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM
EDE2108ABSE-5C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM
EDE2108ABSE-6E-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:2G bits DDR2 SDRAM