參數(shù)資料
型號: EDE2108ABSE-5C-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 2G bits DDR2 SDRAM
中文描述: 256M X 8 DDR DRAM, 0.5 ns, PBGA68
封裝: ROHS COMPLIANT, FBGA-68
文件頁數(shù): 3/81頁
文件大?。?/td> 604K
代理商: EDE2108ABSE-5C-E
EDE2104ABSE, EDE2108ABSE
Preliminary Data Sheet E1196E10 (Ver. 1.0)
3
Pin Configurations
/xxx indicates active low signal.
VDD
1
(NC)*
VDDQ
(NC)*
VDDL
VSS
VDD
2
N(NC)*
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
3
VSS
D(DM)*
VDDQ
DQ3
VSS
/WE
BA1
A1
A5
A9
A14
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
/RAS
/CAS
A2
A6
A11
NC
8
/DQS
VSSQ
DQ0
VSSQ
CK
/CK
/CS
A0
A4
A8
A13
9
VDDQ
(NC)*
VDDQ
(NC)*
VDD
VDD
VSS
(Top view)
68-ball FBGA
(
×
8,
×
4 organization)
Note: ( )* marked pins are for
×
4 organization.
BA2
ODT
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
NC
NC
NC
NC NC NC
Pin name
Function
Pin name
Function
A0 to A14
Address inputs
ODT
ODT control
BA0, BA1, BA2
Bank select
VDD
Supply voltage for internal circuit
DQ0 to DQ7
Data input/output
VSS
Ground for internal circuit
DQS, /DQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
RDQS, /RDQS
Differential data strobe for read
VSSQ
Ground for DQ circuit
/CS
Chip select
VREF
Input reference voltage
/RAS, /CAS, /WE
Command input
VDDL
Supply voltage for DLL circuit
CKE
Clock enable
VSSDL
Ground for DLL circuit
CK, /CK
Differential clock input
NC*
1
No connection
DM
Write data mask
NU*
2
Not usable
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
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