參數資料
型號: EDE2508ABSE
廠商: Elpida Memory, Inc.
英文描述: 256M bits DDR2 SDRAM
中文描述: 256M比特DDR2 SDRAM內存
文件頁數: 7/66頁
文件大?。?/td> 708K
代理商: EDE2508ABSE
EDE2508ABSE, EDE2516ABSE
Preliminary Data Sheet E0573E30 (Ver. 3.0)
7
DC Characteristics 1 (TC = 0
°
C to +85
°
C, VDD, VDDQ = 1.8V
±
0.1V)
max.
×
8
Unit
Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
tCK = tCK (IDD);
CKE is L;
Other control and
address bus inputs are
STABLE;
Data bus inputs are
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Grade
×
16
-6C, -6E 62
62
Operating current
(ACT-PRE)
IDD0
-5C
58
58
mA
-6C, -6E 72
72
Operating current
(ACT-READ-PRE)
IDD1
-5C
70
70
mA
-6C, -6E 6
6
Precharge power-down
standby current
IDD2P
-5C
6
6
mA
-6C, -6E 15
15
Precharge quiet standby
current
IDD2Q
-5C
14
14
mA
-6C, -6E 18
18
Idle standby current
IDD2N
-5C
16
16
mA
-6C, -6E 26
26
IDD3P-F
-5C
22
22
mA
Fast PDN Exit
MRS(12) = 0
-6C, -6E 20
20
Active power-down
standby current
IDD3P-S
-5C
15
15
mA
Slow PDN Exit
MRS(12) = 1
-6C, -6E 50
50
Active standby current
IDD3N
-5C
45
45
mA
-6C, -6E 140
160
Operating current
(Burst read operating)
IDD4R
-5C
120
130
mA
-6C, -6E 150
180
Operating current
(Burst write operating)
IDD4W
-5C
130
140
mA
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EDE2508ABSE-5C-E 256M bits DDR2 SDRAM
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參數描述
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