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參數(shù)資料
| 型號： | EDE2508ABSE |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 256M bits DDR2 SDRAM |
| 中文描述： | 256M比特DDR2 SDRAM內(nèi)存 |
| 文件頁數(shù)： | 8/66頁 |
| 文件大?。?/td> | 708K |
| 代理商： | EDE2508ABSE |
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EDE2508ABSE, EDE2516ABSE
Preliminary Data Sheet E0573E30 (Ver. 3.0)
8
max.
Parameter
Symbol
Grade
×
8
×
16
Unit
Test condition
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self Refresh Mode;
CK and /CK at 0V;
CKE
≤
0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
1
×
tCK
(IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1
×
tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
-6C, -6E 120
120
Auto-refresh current
IDD5
-5C
115
115
mA
6
6
Self-refresh
current
IDD6
mA
-6C, -6E 190
210
Operating current
(Bank interleaving)
IDD7
5C
180
190
mA
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤
VIL (AC) (max.)
H is defined as VIN
≥
VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
DDR2-533
Parameter
4-4-4
5-5-5
4-4-4
CL(IDD)
4
5
4
tRCD(IDD)
12
15
15
tRC(IDD)
57
60
60
tRRD(IDD)
×
8
7.5
7.5
7.5
tCK(IDD)
3
3
3.75
tRAS(min.)(IDD)
45
45
45
tRAS(max.)(IDD)
70000
70000
70000
tRP(IDD)
12
15
15
tRFC(IDD)
75
75
75
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDE2508ABSE-5C-E | 256M bits DDR2 SDRAM |
| EDE2516ABSE-5C-E | 256M bits DDR2 SDRAM |
| EDE2508ABSE-6C-E | 256M bits DDR2 SDRAM |
| EDE2516ABSE-6C-E | 256M bits DDR2 SDRAM |
| EDE2508ABSE-6E-E | 256M bits DDR2 SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDE2508ABSE-5C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
| EDE2508ABSE-6C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
| EDE2508ABSE-6E-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM |
| EDE2508ABSE-GE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM for HYPER DIMM |
| EDE2508ABSE-GE-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M bits DDR2 SDRAM for HYPER DIMM |
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