參數(shù)資料
型號(hào): EDE2516ABSE-GE-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M bits DDR2 SDRAM for HYPER DIMM
中文描述: 16M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝: ROHS COMPLIANT, FBGA-84
文件頁(yè)數(shù): 1/66頁(yè)
文件大小: 708K
代理商: EDE2516ABSE-GE-E
Document No. E0573E30 (Ver. 3.0)
Date Published May 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
PRELIMINARY DATA SHEET
256M bits DDR2 SDRAM
EDE2508ABSE (32M words
×
8 bits)
EDE2516ABSE (16M words
×
16 bits)
Description
The EDE2508ABSE is a 256M bits DDR2 SDRAM
organized as 8,388,608 words
×
8 bits
×
4 banks.
It is packaged in 60-ball FBGA (
μ
BGA
) package.
The EDE2516ABSE is a 256M bits DDR2 SDRAM
organized as 4,194,304 words
×
16 bits
×
4 banks.
It is packaged in 84-ball FBGA (
μ
BGA) package.
Features
Power supply: VDD, VDDQ
=
1.8V
±
0.1V
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8
μ
s at 0
°
C
TC
+
85
°
C
3.9
μ
s at
+
85
°
C
<
TC
+
95
°
C
SSTL_18 compatible I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making
×
8
organization compatible to
×
4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA (
μ
BGA) package with lead free solder
(Sn-Ag-Cu)
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