參數(shù)資料
型號: EDE2516ABSE-GE-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M bits DDR2 SDRAM for HYPER DIMM
中文描述: 16M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝: ROHS COMPLIANT, FBGA-84
文件頁數(shù): 13/66頁
文件大?。?/td> 708K
代理商: EDE2516ABSE-GE-E
EDE2508ABSE, EDE2516ABSE
Preliminary Data Sheet E0573E30 (Ver. 3.0)
13
-6C, -6E
-5C
Frequency (Mbps)
667
533
Parameter
Symbol
min.
max.
min.
max.
Unit
Notes
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to precharge command
tRAS
45
70000
45
70000
ns
Active to auto-precharge delay
Active bank A to active bank B
command period
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command delay
Internal read to precharge command
delay
Exit self refresh to a non-read command tXSNR
tRAP
tRCD min.
tRCD min.
ns
tRRD
7.5
7.5
ns
tWR
15
(tWR/tCK)
+
(tRP/tCK)
7.5
15
(tWR/tCK)
+
(tRP/tCK)
7.5
ns
tDAL
tCK
1
tWTR
ns
tRTP
7.5
7.5
ns
tRFC
+
10
tRFC
+
10
ns
Exit self refresh to a read command
Exit precharge power down to any non-
read command
Exit active power down to read
command
Exit active power down to read
command
(slow exit/low power mode)
CKE minimum pulse width (high and
low pulse width)
Output impedance test driver delay
Auto refresh to active/auto refresh
command time
Average periodic refresh interval
(0
°
C
TC
+85
°
C)
(+85
°
C
<
TC
+95
°
C)
Minimum time clocks remains ON after
CKE asynchronously drops low
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
tXSRD
200
200
tCK
tXP
2
2
tCK
tXARD
2
2
tCK
3
tXARDS
7
AL
6
AL
tCK
2, 3
tCKE
3
3
tCK
tOIT
0
12
0
12
ns
tRFC
75
75
ns
tREFI
7.8
7.8
μ
s
tREFI
tIS
+
tCK
+
tIH
3.9
tIS
+
tCK
+
tIH
3.9
μ
s
tDELAY
ns
DQS
/DQS
tDS
tDH
tDS
tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
CK
/CK
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
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