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參數(shù)資料
| 型號： | EL4511CUZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | IC VID SYNC SEPARATR HDTV 24QSOP |
| 標準包裝： | 250 |
| 類型： | 同步分離器 |
| 應用： | HDTV，投影儀，機頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
18
FN7009.8
November 12, 2010
Video Lock and Level Indicators
Loss of video signal can be detected by monitoring the
SYNCLOCK pin 3. This pin goes high once the sync
separator has detected a valid sync signal and goes low if
this signal is lost for more than 20 successive lines. (Serial
Mode) This signal is also available at register 14 pin 5. Other
lock acquisition signals available from the system are listed
in Table 4.
The sync tip amplitude is buffered with a nominal gain of
2.15 to produce a positive, ground-referenced signal on the
LEVEL pin. This output can be used for AGC applications.
Decode Mode
In order to allow more flexibility when operating without a
serial interface, the XTAL and XTALN pins are decoded by
default to enable four control modes. These modes could be
used to over-ride sync type used. See Table 2 for details.
(Serial Mode) The all-signal type allowed mode is the same
as the default mode when the crystal oscillator is enabled
(set bit 6 of Reg9 to 1) except the countsPerField function is
disabled in Reg13 and Reg14.
The bi-level mode is for bi-level sync only, such as NTSC
and PAL. The tri-level mode is for tri-level sync only, such as
HDTV signals. The VGA only mode is for computer digital
types of signals signal only.
Applications Examples
The following examples show how a system may be
configured to operate the EL4511.
Application 1 (minimum circuitry application)
In this example, the requirement is for vertical and horizontal
timing to be generated from either an NTSC/PAL composite
video waveform, or a computer generated image with
separate TTL level syncs.
The EL4511 has the advantage that the sync separation is
carried out over a wide frequency range without the need to
adjust "RSET" as required by earlier generations of sync
separators.
As there is no Microcontroller connected in this example,
there is no need for a XTAL at pins 1 & 24. These pins are
tied low, this enables the EL4511 to check for either type of
input signal (See Table 2 for details.)
The internal pull-up resistors on XTAL & XTALN are very
high, these pins should use 10k
Ω pull-up/down to operate
when not using a crystal.
By default, the EL4511 will wake up with Register 9, bit 6 set
to Low. This will allow the use of logic levels on pins 1 & 24
to drive register1, bits 5:3 and register 2 bit 0 into the
combinations shown in Table 2.
(Serial Mode) To define the mode through the serial
interface, the register 9, bit 6 must be set to High, the logic
levels on pins 1 & 24 are no longer valid; (most likely now
being an AC signal for the reference clock).
FIGURE 8. APPLICATIONS DRAWING 1
TABLE 2. MODE CONTROL USING PINS 1 & 24
ENXTAL
PIN 1
XTAL
PIN 24
XTALN
MODE
CONTROL
DESCRIPTION
Register9
b 6
Register1
b5 b4 b3
0
0 0 0
All signals
enabled
0
1
0 1 1
Tri-Level Only
0
1
0
1 0 1
Bi-Level Only
0
1
1 1 1
VGA only
1
X
Set by
Serial I/F
Crystal Oscillator
is operational
9
XTALN
11
10
4
1
24
XTAL
PDWN
SYNCIN
VERTIN
HIN
8
GNDD1
13
GNDA2
17
GNDD2
6
SCL
7
SDA
14
18
15
VCCA1
VCCD
VCCA2
16
+
22
21
GNDA2
VERTOUT
HOUT
4.7F
0.1F
75
Ω
75
Ω
75
Ω
100nF
+5V
0.1F
TTL
HORIZ
SYNCS
TTL
VERT
SYNCS
VERT
TIMING TO
SYSTEM
HORIZ
TIMING TO
SYSTEM
10k
Ω
EL4511
EL4511
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