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參數(shù)資料
| 型號(hào)： | EL4511CUZ-T7A |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 15/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VID SYNC SEPARATR HDTV 24QSOP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類(lèi)型： | 同步分離器 |
| 應(yīng)用： | HDTV，投影儀，機(jī)頂盒 |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 帶卷 (TR) |
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22
FN7009.8
November 12, 2010
TABLE 5. SERIAL INTERFACE REGISTER BIT ALLOCATIONS
REGISTER
NUMBER
REGISTER
BIT
SIGNAL NAME
TYPE
RESET
VALUE
DESCRIPTION AND COMMENTS
1
General Control Reg 1
R/W
00h
7
General Reset
0
Software reset. Does not affect serial interface.
6
AlwaysEnOutputs
0
Overrides internal qualification of outputs.
5:3
ModeCtrl
0
Sync acquisition. Selects input signal. See Table 3.
2
General Control Reg 2
R/W
10h
5
Select Fixed Slicing (no S/H)
0
Necessary for SECAM. May be useful for VCRs.
4
FILTER_ENABLED
1
Set Hi to include digital filter on horizontal input.
1
OE_MODE
0
Set Hi for Odd/Even changes on rising edge of vertical.
3VBLANK Control Reg 1
R/W
90h
7
EnVBlank
1
Enables vertical blank interval detection algorithm.
6:0
VSTPlusBP
10h
Number of lines after vertical sync time.
4VBLANK & Polarity Ctrl
R/W
4Fh
7:4
VFrontPorch
4h
Number of lines before vertical sync time.
3
DefaultHPolarity
1
HIN polarity on reset if EnHpolarityDet = Lo.
2
DefaultVPolarity
1
VERTIN polarity on reset and if EnVpolarityDet = Lo.
1
EnHPolarityDet
1
Allows EL4511 to detect and set polarity on HIN.
0
EnVPolarityDet
1
Allows EL4511 to detect and set polarity on VERTIN.
6
Oscillator Control 2
R/W
22h
7:6
CMuxCtrl <1:0>
0
7VBLANK O/P Reg 1
R
Only valid if VBLANK circuit is enabled
7:0
LinesPerFrame <7:0>
-
Least significant byte of lines per frame count.
8VBLANK O/P Reg 2 & Misc
R
80h
7:4
LinesPerFrame <11:8>
-
Most significant 4 bits of lines per frame count.
3
En50Slice
-
Indicates sample and hold front end is being used.
2
LPFValid
-
Indicates lines per frame has been updated.
1
progressive
-
Not valid for certain types of composite sync.
0
tri-level detect
-
Only valid if tri-level sync detected.
9
Analog Control Reg 1
R/W
6
ENXTAL
0
Set Hi to enable crystal oscillator.
5
ENLEVELBLANKING
0
Set Hi to enable VLEVEL when not locked.
4
ENLEVEL
0
Set Hi to disable VLEVEL output.
3
ENSYCLAMP
0
Set Hi to disable “soft” sync tip clamping in SYNCIN.
2ENALOS
0
Set Hi to disable analog loss of signal feature.
1ENRVIDEO
0
Set Hi to disable internal biasing on SYNCIN (passive resistor
or soft clamp.)
0
PWRSAVE
0
Set Hi to put the analog circuit into powersave mode.
13
Absolute Timing Ref 1
R
7:0
CountsPerField <7:0>
-
Crystal clock periods per field: L.S. Byte. (see description)
14
Absolute Timing Ref 2 & Misc
R
EL4511
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