參數(shù)資料
型號(hào): EL4584CSZ-EVAL
廠商: Intersil
文件頁(yè)數(shù): 7/15頁(yè)
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR EL4584
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),PLL
嵌入式:
已用 IC / 零件: EL4584CSZ
主要屬性: 適用于高達(dá) 36 MHz 的視頻
次要屬性: 5V 電源,< 2ns 抖動(dòng)(VCXO)
已供物品:
15
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7174.3
May 9, 2008
EL4584
Plastic Dual-In-Line Packages (PDIP)
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
INCHES
TOLERANCE
NOTES
PDIP8
PDIP14
PDIP16
PDIP18
PDIP20
A
0.210
MAX
A1
0.015
MIN
A2
0.130
±0.005
b
0.018
±0.002
b2
0.060
+0.010/-0.015
c
0.010
+0.004/-0.002
D
0.375
0.750
0.890
1.020
±0.010
1
E
0.310
+0.015/-0.010
E1
0.250
±0.005
2
e
0.100
Basic
eA
0.300
Basic
eB
0.345
±0.025
L
0.125
±0.010
N
8
14
16
18
20
Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
D
L
A
e
b
A1
NOTE 5
A2
SEATING
PLANE
L
N
PIN #1
INDEX
E1
12
N/2
b2
E
eB
eA
c
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