參數(shù)資料
型號： ELANSC410-66AI
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述： 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PBGA292
封裝： PLASTIC, BGA-292
文件頁數(shù)： 111/132頁
文件大小： 2400K
代理商： ELANSC410-66AI
élanSC400 and élanSC410 Microcontrollers Data Sheet
111
Table 39.
VESA Local Bus Cycles
Symbol
Parameter Description
33-MHz
External Bus
Min
27
14
14
3
3
Unit
Max
t1
t2
t3
t4
t5
VL_LCLK period
VL_LCLK pulse High
VL_LCLK pulse Low
VL_ADS delay from VL_LCLK
SA25–SA2, VL_BE3–VL_BE0, VL_M/IO, VL_W/R, VL_D/C delay from
VL_LCLK
VL_BLAST valid from VL_LCLK
VL_LDEV valid from SA25–SA2, VL_BE3–VL_BE0, VL_M/IO, VL_W/R,
VL_D/C
VL_LDEV setup to VL_LCLK
VL_LRDY, VL_BRDY setup to VL_LCLK
VL_LRDY, VL_BRDY (VL-Bus target is driver) hold from VL_LCLK
VL_LRDY (VL-Bus target is driver) three stated from VL_LCLK
Read data setup to VL_LCLK
Read data hold from VL_CLK
Write data delay from VL_CLK
ns
ns
ns
ns
ns
18
18
t6
t7
3
18
20
ns
ns
t8
1
t9
t10
t11
t12
t13
t14
Notes:
1. LDEV is checked on the following rising edge of the CPU clock (not shown, up to 100 MHz) from the assertion of ADS. ADS
can assert a minimum of 20 ns after address change.
15
12
0
ns
ns
ns
ns
ns
ns
ns
0
5
0
3
18
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