參數(shù)資料
型號(hào)： ELANSC410-66AI
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述： 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PBGA292
封裝： PLASTIC, BGA-292
文件頁數(shù)： 81/132頁
文件大小： 2400K
代理商： ELANSC410-66AI
élanSC400 and élanSC410 Microcontrollers Data Sheet
81
Figure 9.
Graphics Dot Clock PLL Block Diagram
High-Speed PLL
The High-Speed PLL generates a 66.3552-MHz clock
for the DRAM controller. Figure 10 on page 82 shows
the block diagram for the High-Speed PLL. The input to
the High-Speed PLL is the output of the Low-Speed
PLL divided by five. The feedback divider is nine, which
results in an output frequency (Fo) of 66.3552 MHz.
This frequency is divided by 2 in the PMU to provide the
33-MHz input for the PLL in the CPU core.
Band Gap Block
The band gap reference circuit generates the bias cur-
rents for the four PLLs and provides a 2.4-V reference
source for the RTC voltage monitor. The current
sources, constant over V
CC
, temperature, and process
variations, are used by the four PLL charge pumps for
adjusting the PLL operating frequency. The 2.4-V refer-
ence voltage is used by the RTC voltage monitor to de-
tect a low backup battery voltage level.
RTC Voltage Monitor
The voltage monitor for the RTC block is shown in
Figure 11 on page 82. Its functions are to provide a
reset signal to the RTC block when it detects a low
backup battery voltage, and to provide an early warn-
ing signal when the system is powering down.
The internal RTC reset signal is asserted on power-up
if the back-up battery voltage drops below 2.4 V. The
one shot prevents multiple resets during power-on.
An internal power-down signal is used by the RTC to
isolate the RTC core from the rest of the
microcontroller. The RTC voltage monitor uses the
RESET assertion to detect a power-down. For proper
operation, RESET and V
CC
must follow the timing in
Figure 12 on page 83.
Down
Up
Charge
Pump
Loop
Filter
VCCA
36.864 MHz
Phase
Detector
Vc
20.736–
36.864 MHz
Fo
Ff
Fr
Divider
(9–16)
/16
VCO
PLLRATIO[2–0]
Programmable
Internal
External
C
1
R
C
2
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