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參數(shù)資料
| 型號(hào)： | ELANSC410-66AI |
| 廠(chǎng)商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers |
| 中文描述： | 32-BIT, FLASH, 66 MHz, MICROCONTROLLER, PBGA292 |
| 封裝： | PLASTIC, BGA-292 |
| 文件頁(yè)數(shù)： | 45/132頁(yè) |
| 文件大?。?/td> | 2400K |
| 代理商： | ELANSC410-66AI |
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élanSC400 and élanSC410 Microcontrollers Data Sheet
45
MA10
MA11
MWE
RAS0
RAS1
ROMCS0
ROMCS1
ROMRD
ROMWR
C13
A16
A11
C15
D14
R18
T19
V20
U19
O
O
O
O
O
O
O
O
O
C–E
3
C–E
3
C–E
3
C–E
3
C–E
3
B
B
B
B
70
70
70
50
50
50
50
50
50
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
L
L
H
H
H
H
H
H
H
O
O
O
O
O
O
O
O
O
TS-PD
TS-PD
H[TS-PD]
O[L][TS-PD]
O[L][TS-PD]
H[TS-PD][TS]
H[TS-PD][TS]
H[TS-PD][TS]
H[TS-PD][TS]
8
8
A
A
A
B
B
B
B
2
2
2
9
S
S
S
S
9
9
9
Notes:
1.
Pin states for D31–D16 are listed in Table 6 on page 42.
2. RAS3–RAS0, CASH3–CASH0, CASL3–CASL0, and MWE Suspend state of the pins:
–The RAS and CAS signals remain active if the DRAM interface is configured for CAS-before-RAS refresh in Suspend mode.
–The RAS and CAS signals will be Low if the DRAM is configured for self-refresh in Suspend mode.
–Will be three-stated with a pulldown resistor if the DRAM interface is programmed to be disabled so the DRAM can be
powered down (Power-Down Group A).
–Will not be affected by this when the RAS and CAS signals that share pins with other functions (RAS3–RAS2, CASH3–
CASH2, and CASL3–CASL2) are not enabled to come out of the chip.
–The MWE signal will be driven out High (deasserted) when the DRAM is programmed to be left powered (Power-Down
Group A).
Summary:
These pins have built-in pulldown resistors that are invoked by:
–Suspend mode and DRAM interface programmed for power-down in Suspend (Power-Down Group A), and the pins are
enabled as RAS/CAS for RAS3–RAS2, CASH3–CASH2, and CASL3–CASL2.
3. C, D, and E output drives are programmable.
4. The data bus D15–D0 has built-in pulldown resistors that are invoked when the data bus signals are inputs.
5. Memory Address MA12 Suspend state of the pin:
Will be three-stated with a pulldown resistor. This will work for CAS-before-RAS refresh, self-refresh, and the DRAM powered down.
Summary:
This pin has a built-in pulldown resistor that is invoked by Suspend mode.
6. Memory Address MA4–MA0 pins are shared with the power-on configuration signals so the reset state of the pins has a pull-
down resistor on these signals.
This default configuration will choose: not test mode and an 8-bit ROM/Flash memory accessed by ROMCS0 with the SD
buffer-control signals disabled. The pulldown resistors are from 50 K to 150 K; they need to be overridden by pullup resistors
on the board if other configurations are needed.
These pulldown resistors are disabled after reset; they are not active during normal chip operation.
For configuration signals CFG0, CFG1, CFG2, and CFG3, if the system uses the default configuration, the pulldown resistors
will be active again in Suspend mode. If external pullup resistors are used on the board for a different configuration, the pins
with external pullups will three-state in Suspend mode without pulldown resistors.
The reserved signal on MA4 is only used for AMD testing; it should not be pulled up on the system design. This pin will always
go to three-state with a pulldown resistor in Suspend mode.
Summary:
Each pin has a built-in pulldown resistor that is invoked by:
–Reset
–Suspend mode and the configuration pin being Low during reset (for CFG3–CFG0).
–Suspend mode for the reserved signal on MA4.
Table 7.
Pin State Table—Memory Interface
1
(Continued)
Signal Name
[Alternate
Function]
Pin
#
Type
Output
Drive
Max
Load
(pF)
Supply
Reset
State
Normal
Operation
Suspend
State
Power
Down
Group
Note
5 V
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