參數(shù)資料
型號(hào)： EM39LV80055RM
廠商： ELAN Microelctronics Corp .
英文描述： IC 8BIT DUAL BUS TXRX 3ST24TSSOP
中文描述： 分位（512Kx16）閃存
文件頁(yè)數(shù)： 5/25頁(yè)
文件大?。?/td> 295K
代理商： EM39LV80055RM
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 5 of
25
EM39LV800 Device Operation
Operation
CE#
OE#
WE#
DQ
Address
Read
V
IL
V
IL
V
IH
D
OUT
A
IN
Program
V
IL
V
IH
V
IL
D
IN
A
IN
Erase
V
IL
V
IH
V
IL
X
*
Sector or Block address, XXH for
Chip-Erase
Standby
V
IH
X
X
High Z
X
Write Inhibit
X
V
IL
X
High Z/D
OUT
X
Write Inhibit
X
X
V
IH
High Z/D
OUT
X
Software Mode
V
IL
V
IL
V
IH
See Table 3
Product
Identification
*
X can be V
IL
or V
IH
, but no other value.
Table 2:
EM39LV800 Device Operation
Write Command/Command Sequence
The EM39LV800 provides two software methods to detect the completion of a Program or
Erase cycle in order to optimize the system write cycle time. The software detection includes
two status bits
:
Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode
is enabled after the rising edge of WE#, which initiates the internal Program or Erase
operation. The actual completion of the write operation is asynchronous with the system;
therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid
data may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious
rejection, when an erroneous result occurs, the software routine should include an additional
two times loop to read the accessed location. If both reads are valid, then the device has
completed the write cycle, otherwise the rejection is valid.
Chip Erase
The EM39LV800 provides Chip-Erase feature, which allows the entire memory array to be
erased to logic “1” state. The Chip-Erase operation is initiated by executing a six-byte
command sequence with Chip-Erase command (10H) at address 5555H in the last byte
sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#,
whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and
Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and
Figure 17 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
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