- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362666 > EM39LV80070M (ELAN Microelctronics Corp .) DDR-I, 13/26-Bit Registered Buffer PDF資料下載
參數(shù)資料
| 型號： | EM39LV80070M |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | DDR-I, 13/26-Bit Registered Buffer |
| 中文描述： | 分位（512Kx16）閃存 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 295K |
| 代理商： | EM39LV80070M |
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 4 of
25
Device Operation
The EM39LV800 uses Commands to initiate the memory operation functions. The
Commands are written to the device by asserting WE# Low while keeping CE# Low. The
address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data
bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the EM39LV800 is controlled by CE# and OE#. Both have to be Low
for the system to obtain data from the outputs. CE# is used for device selection. When CE#
is high, the chip is deselected and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for
further details.
Word Program
The EM39LV800 is programmed on a word-by-word basis. Before programming, the sector
where the word is located must be erased completely. The Program operation is
accomplished in three steps
:
The first step is a three-byte load sequence for Software Data Protection.
The second step is to load word address and word data. During the Word Program
operation, the addresses are latched on the falling edge of either CE# or WE#, whichever
occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever
occurs first.
The third step is the internal Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated,
will be completed within 20 μs. See Figures 2 and 3 for WE# and CE# controlled
Program operation timing diagrams respectively and Figure 15 for flowchart.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform additional tasks. Any command
issued during the internal Program operation is ignored.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EM39LV80070Y | 8M Bits (512Kx16) Flash Memory |
| EM39LV80055RH | IC, DIGITAL, OCTAL BUS XCEIVER & 3.3V TO 5.0V, SHFTR BIDRCNTL, V XLATOR, 24PIN T |
| EM39LV80055RM | IC 8BIT DUAL BUS TXRX 3ST24TSSOP |
| EM39LV80055RY | 8M Bits (512Kx16) Flash Memory |
| EM4100B5WS11 | Read Only Contactless Identification Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EM39LV80070Y | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:8M Bits (512Kx16) Flash Memory |
| EM39LV80090D | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:8M Bits (512Kx16) Flash Memory |
| EM39LV80090H | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:8M Bits (512Kx16) Flash Memory |
| EM39LV80090M | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:8M Bits (512Kx16) Flash Memory |
| EM39LV80090Y | 制造商:EMC 制造商全稱:ELAN Microelectronics Corp 功能描述:8M Bits (512Kx16) Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。