參數(shù)資料
型號(hào)： Embedded Pentium 166
廠商： Intel Corp.
英文描述： 32 Bit Embedded Pentium Processor(32位嵌入式奔騰處理器)
中文描述： 32位嵌入式奔騰處理器（32位嵌入式奔騰處理器）
文件頁(yè)數(shù)： 18/42頁(yè)
文件大?。?/td> 882K
代理商： EMBEDDED PENTIUM 166
Embedded Pentium
Processor
18
Datasheet
DP7–DP0
I/O
These are the
data parity
pins for the processor. There is one for each byte of the
data bus. They are driven by the Pentium processor with even parity information on
writes in the same clock as write data. Even parity information must be driven back
to the processor on these pins in the same clock as the data to ensure that the
correct parity check status is indicated by the Pentium processor. DP7 applies to
D63–D56, DP0 applies to D7–D0.
[DPEN#]
PICD0
I/O
Dual processing enable
is an output of the Dual processor and an input of the
Primary processor. The Dual processor drives DPEN# low to the Primary processor
at RESET to indicate that the Primary processor should enable dual processor
mode. DPEN# may be sampled by the system at the falling edge of RESET to
determine if the dual-processor socket is occupied. DPEN# shares a pin with PICD0.
EADS#
I
The
external address strobe
signal indicates that a valid external address has
been driven onto the processor address pins to be used for an inquire cycle.
EWBE#
I
The
external write buffer empty
input, when inactive (high), indicates that a write
cycle is pending in the external system. When the processor generates a write, and
EWBE# is sampled inactive, the processor holds off all subsequent writes to all E- or
M-state lines in the data cache until all write cycles have completed, as indicated by
EWBE# being active.
FERR#
O
The
floating-point error
pin is driven active when an unmasked floating-point error
occurs. FERR# is similar to the ERROR# pin on the Intel387 math coprocessor.
FERR# is included for compatibility with systems using DOS-type floating-point error
reporting. FERR# is never driven active by the Dual processor.
FLUSH#
I
When asserted, the
cache flush
input forces the processor to write back all
modified lines in the data cache and invalidate its internal caches. A Flush
Acknowledge special cycle is generated by the processor to indicate completion of
the write back and invalidation.
When FLUSH# is sampled low when RESET transitions from high to low, three-state
test mode is entered.
If two Pentium processors are operating in dual processing mode and FLUSH# is
asserted, the Dual processor performs a flush first (without a flush acknowledge
cycle), then the Primary processor performs a flush followed by a flush acknowledge
cycle.
When the FLUSH# signal is asserted in dual processing mode, it must be
deasserted at least one clock prior to BRDY# of the FLUSH Acknowledge cycle to
avoid DP arbitration problems.
FRCMC#
I
The
functional redundancy checking master/checker
mode input is used to
determine whether the processor is configured in master mode or checker mode.
When configured as a master, the processor drives its output pins as required by the
bus protocol. When configured as a checker, the processor three-states all outputs
(except IERR# and TDO) and samples the output pins.
The configuration as a master/checker is set after RESET and may not be changed
other than by a subsequent RESET.
HIT#
O
The
inquire cycle hit/miss
indication is driven to reflect the outcome of an inquire
cycle. If an inquire cycle hits a valid line in either the processor data or instruction
cache, this pin is asserted two clocks after EADS# is sampled asserted. If the
inquire cycle misses the processor cache, this pin is negated two clocks after
EADS#. This pin changes its value only as a result of an inquire cycle and retains its
value between the cycles.
HITM#
O
The
inquire cycle hit/miss to a modified line
output is driven to reflect the
outcome of an inquire cycle. It is asserted after an inquire cycle that results in a hit to
a modified line in the data cache. It is used to inhibit another bus master from
accessing the data until the line is completely written back.
The pins are classified as Input or Output based on their function in Master Mode. See the Pentium
Processor
Family Developer’s Manual
(order number 273204) for more information.
Table 4. Pin Quick Reference (Sheet 3 of 5)
Symbol
Type
Name and Function
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