參數(shù)資料
型號： ENC424J600-I/ML
廠商： Microchip Technology
文件頁數(shù)： 66/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 44-QFN
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 45
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 44-QFN（8x8）
包裝： 管件
產(chǎn)品目錄頁面： 684 (CN2011-ZH PDF)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
PIC18F2220/2320/4220/4320
DS39599G-page 156
2007 Microchip Technology Inc.
17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
MSSP Control Register 1 (SSPCON1)
MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
REGISTER 17-1:
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
R-0
SMP
CKE
D/A
PS
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6
CKE: SPI Clock Edge Select bit
When CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
When CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5
D/A: Data/Address bit
Used in I2C mode only.
bit 4
P: Stop bit
Used in I2C mode only.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
R/W: Read/Write Information bit
Used in I2C mode only.
bit 1
UA: Update Address bit
Used in I2C mode only.
bit 0
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ENC424J600-IPT 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface
ENC424J600T-I/ML 功能描述:以太網(wǎng) IC 10/100 Base-T Stand alone Ethernet Ctrlr RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
ENC424J600T-I/PT 功能描述:外圍驅(qū)動器與原件 - PCI 10/100 Base-T Stand alone Ethernet Ctrlr RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ENC424J600T-IML 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface
ENC424J600T-IPT 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:Stand-Alone 10/100 Ethernet Controller with SPI or Parallel Interface
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