參數(shù)資料
型號： ENC624J600T-I/PT
廠商： Microchip Technology
文件頁數(shù)： 149/168頁
文件大小： 0K
描述： IC ETHERNET CTRLR W/SPI 64-TQFP
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,200
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
2007 Microchip Technology Inc.
DS39599G-page 79
PIC18F2220/2320/4220/4320
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset, during normal operation. In
these situations, users can check the WRERR bit and
rewrite the location.
6.6
Flash Program Operation During
Code Protection
tection”) for details on code protection of Flash
program memory.
TABLE 6-2:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BCF
INTCON,GIE
; disable interrupts
MOVLW
55h
; required sequence
MOVWF
EECON2
; write 55H
MOVLW
AAh
MOVWF
EECON2
; write AAH
BSF
EECON1,WR
; start program (CPU stall)
NOP
BSF
INTCON,GIE
; re-enable interrupts
DECFSZ COUNTER_HI
; loop until done
GOTO
PROGRAM_LOOP
BCF
EECON1,WREN
; disable write to memory
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
TBLPTRU
—
bit 21
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
--00 0000 --00 0000
TBPLTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 0000 0000
TBLPTRL
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
TABLAT
Program Memory Table Latch
0000 0000 0000 0000
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
EECON2
EEPROM Control Register 2 (not a physical register)
—
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 uu-0 u000
IPR2
OSCFIP
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP
11-1 1111 ---1 1111
PIR2
OSCFIF
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF
00-0 0000 ---0 0000
PIE2
OSCFIE
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE
00-0 0000 ---0 0000
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
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