
Altera Corporation
3
Preliminary Information
Cyclone FPGA Family Data Sheet
Table of
Contents
Introduction........................................................................................................1
Features...............................................................................................................1
Table of Contents...............................................................................................3
Functional Description......................................................................................4
Logic Array Blocks.............................................................................................6
Logic Elements...................................................................................................9
MultiTrack Interconnect .................................................................................17
Embedded Memory.........................................................................................23
Global Clock Network & Phase-Locked Loops...........................................34
I/O Structure....................................................................................................44
Power Sequencing & Hot Socketing .............................................................60
IEEE Std. 1149.1 (JTAG) Boundary Scan Support.......................................60
SignalTap II Embedded Logic Analyzer......................................................65
Configuration...................................................................................................65
Operating Conditions......................................................................................67
Power Consumption........................................................................................73
Timing Model...................................................................................................73
Software.............................................................................................................93
Device Pin-Outs ...............................................................................................93
Ordering Information......................................................................................93