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參數(shù)資料
| 型號(hào)： | EP1C6T324I6 |
| 廠商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family |
| 中文描述： | 氣旋FPGA系列 |
| 文件頁數(shù)： | 8/94頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | EP1C6T324I6 |
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Altera Corporation
Cyclone FPGA Family Data Sheet
Preliminary Information
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the
labclk1
signal will also use
labclkena1
. If
the LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal will turn off
the LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
With the LAB-wide
addnsub
control signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending on
data.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack
TM
interconnect’s inherent low skew
allows clock and control signal distribution in addition to data.
Figure 4
shows the LAB control signal generation circuit.
Figure 4. LAB-Wide Control Signals
labclkena1
labclk2
labclk1
labclkena2
asyncload
or labpre
syncload
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclr1
labclr2
synclr
addnsub
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