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參數(shù)資料
型號: EP20K100EFC324-2N
廠商: Altera
文件頁數(shù): 48/117頁
文件大小: 0K
描述: IC APEX 20KE FPGA 100K 324-FBGA
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 84
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計: 53248
輸入/輸出數(shù): 246
門數(shù): 263000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 324-BGA
供應商設備封裝: 324-FBGA(19x19)
36
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
f For more information on APEX 20KE devices and CAM, see Application
Driving Signals to the ESB
ESBs provide flexible options for driving control signals. Different clocks
can be used for the ESB inputs and outputs. Registers can be inserted
independently on the data input, data output, read address, write
address, WE, and RE signals. The global signals and the local interconnect
can drive the WE and RE signals. The global signals, dedicated clock pins,
and local interconnect can drive the ESB clock signals. Because the LEs
drive the local interconnect, the LEs can control the WE and RE signals and
the ESB clock, clock enable, and asynchronous clear signals. Figure 24
shows the ESB control signal generation logic.
Figure 24. ESB Control Signal Generation
Note to Figure 24:
(1)
APEX 20KE devices have four dedicated clocks.
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high-speed connection to the ESB) or the MegaLAB interconnect. The
ESB can drive the local, MegaLAB, or FastTrack Interconnect routing
structure to drive LEs and IOEs in the same MegaLAB structure or
anywhere in the device.
RDEN
WREN
INCLOCK
INCLKENA
OUTCLOCK
OUTCLKENA
Dedicated
Clocks
Global
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
2 or 4
4
Local
Interconnect
Local
Interconnect
INCLR OUTCLR
(1)
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