Notes to Tables 4 and 5: (1) I/O counts include dedicated input and c" />
參數(shù)資料
型號(hào): EP20K100EFC324-2N
廠商: Altera
文件頁數(shù): 63/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 100K 324-FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 84
系列: APEX-20K®
LAB/CLB數(shù): 416
邏輯元件/單元數(shù): 4160
RAM 位總計(jì): 53248
輸入/輸出數(shù): 246
門數(shù): 263000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 324-BGA
供應(yīng)商設(shè)備封裝: 324-FBGA(19x19)
Altera Corporation
5
APEX 20K Programmable Logic Device Family Data Sheet
Notes to Tables 4 and 5:
(1)
I/O counts include dedicated input and clock pins.
(2)
APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, and pin-grid array (PGA)
packages.
(3)
This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device
Package Information Data Sheet for detailed package size information.
Table 5. APEX 20K FineLine BGA Package Options & I/O Count
Device
144 Pin
324 Pin
484 Pin
672 Pin
1,020 Pin
EP20K30E
93
128
EP20K60E
93
196
EP20K100
252
EP20K100E
93
246
EP20K160E
316
EP20K200
382
EP20K200E
376
EP20K300E
408
EP20K400
502 (3)
EP20K400E
488 (3)
EP20K600E
508 (3)
588
EP20K1000E
508 (3)
708
EP20K1500E
808
Table 6. APEX 20K QFP, BGA & PGA Package Sizes
Feature
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
Pitch (mm)
0.50
1.27
Area (mm2)
484
924
1,218
1,225
2,025
3,906
Length
× Width
(mm
× mm)
22
× 22
30.4
× 30.4
34.9
× 34.9
35
× 35
45
× 45
62.5
× 62.5
Table 7. APEX 20K FineLine BGA Package Sizes
Feature
144 Pin
324 Pin
484 Pin
672 Pin
1,020 Pin
Pitch (mm)
1.00
Area (mm2)
169
361
529
729
1,089
Length
× Width (mm × mm)
13
× 13
19
× 19
23
× 23
27
× 27
33
× 33
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