參數資料
| 型號： | EP20K100EQC240-1 |
| 廠商： | Altera |
| 文件頁數： | 60/117頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC APEX 20KE FPGA 100K 240-PQFP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 24 |
| 系列： | APEX-20K® |
| LAB/CLB數： | 416 |
| 邏輯元件/單元數： | 4160 |
| RAM 位總計： | 53248 |
| 輸入/輸出數： | 183 |
| 門數： | 263000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應商設備封裝： | 240-PQFP（32x32） |
| 其它名稱： | 544-1863 EP20K100EQC240-1-ND |
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Altera Corporation
47
APEX 20K Programmable Logic Device Family Data Sheet
APEX 20KE devices also support the MultiVolt I/O interface feature. The
APEX 20KE VCCINT pins must always be connected to a 1.8-V power
supply. With a 1.8-V VCCINT level, input pins are 1.8-V, 2.5-V, and 3.3-V
tolerant. The VCCIO pins can be connected to either a 1.8-V, 2.5-V, or 3.3-V
power supply, depending on the I/O standard requirements. When the
VCCIO
pins are connected to a 1.8-V power supply, the output levels are
compatible with 1.8-V systems. When VCCIO pins are connected to a 2.5-V
power supply, the output levels are compatible with 2.5-V systems. When
VCCIO
pins are connected to a 3.3-V power supply, the output high is
3.3 V and compatible with 3.3-V or 5.0-V systems. An APEX 20KE device
is 5.0-V tolerant with the addition of a resistor.
Table 13 summarizes APEX 20KE MultiVolt I/O support.
Notes to Table 13:
(1)
The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO, except for the 5.0-V
input case.
(2)
An APEX 20KE device can be made 5.0-V tolerant with the addition of an external resistor. You also need a PCI
clamp and series resistor.
(3)
When VCCIO = 3.3 V, an APEX 20KE device can drive a 2.5-V device with 3.3-V tolerant inputs.
ClockLock &
ClockBoost
Features
APEX 20K devices support the ClockLock and ClockBoost clock
management features, which are implemented with PLLs. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by sharing resources within the device. The ClockBoost
circuitry allows the designer to distribute a low-speed clock and multiply
that clock on-device. APEX 20K devices include a high-speed clock tree;
unlike ASICs, the user does not have to design and optimize the clock tree.
The ClockLock and ClockBoost features work in conjunction with the
APEX 20K device’s high-speed clock to provide significant improvements
in system performance and band-width. Devices with an X-suffix on the
ordering code include the ClockLock circuit.
The ClockLock and ClockBoost features in APEX 20K devices are enabled
through the Quartus II software. External devices are not required to use
these features.
Table 13. APEX 20KE MultiVolt I/O Support
VCCIO (V)
Input Signals (V)
Output Signals (V)
1.8
2.5
3.3
5.0
1.8
2.5
3.3
5.0
1.8
vv
v
2.5
vvv
v
3.3
vvv
v(3)
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相關代理商/技術參數 |
參數描述 |
|---|---|
| EP20K100EQC240-1ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
| EP20K100EQC240-1N | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 416 Macro 183 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K100EQC240-1X | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 416 Macro 183 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K100EQC240-2 | 功能描述:FPGA - 現場可編程門陣列 CPLD - APEX 20K 416 Macro 183 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP20K100EQC240-2ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA |
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