參數(shù)資料
型號： EP20K200EFI672-2X
廠商： Altera
文件頁數(shù)： 41/117頁
文件大?。?/td> 0K
描述： IC APEX 20KE FPGA 200K 672-FBGA
標準包裝： 40
系列： APEX-20K®
LAB/CLB數(shù)： 832
邏輯元件/單元數(shù)： 8320
RAM 位總計： 106496
輸入/輸出數(shù)： 376
門數(shù)： 404000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 672-BBGA
供應(yīng)商設(shè)備封裝： 672-BGA（27x27）
Altera Corporation
3
APEX 20K Programmable Logic Device Family Data Sheet
■
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
–
Built-in low-skew clock tree
–
Up to eight global clock signals
–
ClockLock feature reducing clock delay and skew
–
ClockBoost feature providing clock multiplication and division
–
ClockShiftTM programmable clock phase and delay shifting
■
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
–
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
–
Bidirectional I/O performance (tCO + tSU) up to 250 MHz
–
LVDS performance up to 840 Mbits per channel
–
Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
–
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
–
Programmable clamp to VCCIO
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
–
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
–
Pull-up on I/O pins before and during configuration
■
Advanced interconnect structure
–
Four-level hierarchical FastTrack Interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
■
Advanced packaging options
–
Available in a variety of packages with 144 to 1,020 pins (see
Tables 4 through 7)
–
FineLine BGA packages maximize board space efficiency
■
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera Quartus II development system for
相關(guān)PDF資料
PDF描述
EP20K100QC240-3V IC APEX 20K FPGA 100K 240-PQFP
EP20K100QC208-3V IC APEX 20K FPGA 100K 208-PQFP
EP20K100EBI356-2X IC APEX 20KE FPGA 100K 356-BGA
ABB65DHAN CONN EDGECARD 130PS R/A .050 SLD
ABB65DHAD CONN EDGECARD 130PS R/A .050 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K200EFI672-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K200EQC208-1 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K200EQC208-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K200EQC208-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K200EQC208-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 832 Macro 136 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*