參數資料
型號: EP20K200EFI672-2X
廠商: Altera
文件頁數: 79/117頁
文件大小: 0K
描述: IC APEX 20KE FPGA 200K 672-FBGA
標準包裝: 40
系列: APEX-20K®
LAB/CLB數: 832
邏輯元件/單元數: 8320
RAM 位總計: 106496
輸入/輸出數: 376
門數: 404000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 672-BBGA
供應商設備封裝: 672-BGA(27x27)
64
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 29. APEX 20KE Device DC Operating Conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
High-level LVTTL, CMOS, or 3.3-V
PCI input voltage
1.7, 0.5
× VCCIO
4.1
V
VIL
Low-level LVTTL, CMOS, or 3.3-V
PCI input voltage
–0.5
0.8, 0.3
× VCCIO
V
VOH
3.3-V high-level LVTTL output
voltage
IOH = –12 mA DC,
VCCIO =3.00 V (11)
2.4
V
3.3-V high-level LVCMOS output
voltage
IOH = –0.1 mA DC,
VCCIO =3.00 V (11)
VCCIO –0.2
V
3.3-V high-level PCI output voltage IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V
0.9
× VCCIO
V
2.5-V high-level output voltage
IOH = –0.1 mA DC,
VCCIO =2.30 V (11)
2.1
V
IOH = –1 mA DC,
VCCIO =2.30 V (11)
2.0
V
IOH = –2 mA DC,
VCCIO =2.30 V (11)
1.7
V
VOL
3.3-V low-level LVTTL output
voltage
IOL = 12 mA DC,
VCCIO =3.00 V (12)
0.4
V
3.3-V low-level LVCMOS output
voltage
IOL = 0.1 mA DC,
VCCIO =3.00 V (12)
0.2
V
3.3-V low-level PCI output voltage IOL = 1.5 mA DC,
VCCIO = 3.00 to 3.60 V
0.1
× VCCIO
V
2.5-V low-level output voltage
IOL = 0.1 mA DC,
VCCIO =2.30 V (12)
0.2
V
IOL = 1 mA DC,
VCCIO =2.30 V (12)
0.4
V
IOL = 2 mA DC,
VCCIO =2.30 V (12)
0.7
V
II
Input pin leakage current
VI = 4.1 to –0.5 V (13)
–10
10
A
IOZ
Tri-stated I/O pin leakage current
VO = 4.1 to –0.5 V (13)
–10
10
A
ICC0
VCC supply current (standby)
(All ESBs in power-down mode)
VI = ground, no load, no
toggling inputs, -1 speed
grade
10
mA
VI = ground, no load, no
toggling inputs,
-2, -3 speed grades
5mA
RCONF
Value of I/O pin pull-up resistor
before and during configuration
VCCIO = 3.0 V (14)
20
50
k
VCCIO = 2.375 V (14)
30
80
k
VCCIO =1.71 V (14)
60
150
k
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