參數(shù)資料
型號(hào): EP20K400EFC672-3N
廠商: Altera
文件頁數(shù): 34/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 400K 672-FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 40
系列: APEX-20K®
LAB/CLB數(shù): 1664
邏輯元件/單元數(shù): 16640
RAM 位總計(jì): 212992
輸入/輸出數(shù): 488
門數(shù): 1052000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 672-BBGA
供應(yīng)商設(shè)備封裝: 672-BGA(27x27)
Altera Corporation
23
APEX 20K Programmable Logic Device Family Data Sheet
Figure 11 shows the intersection of a row and column interconnect, and
how these forms of interconnects and LEs drive each other.
Figure 11. Driving the FastTrack Interconnect
APEX 20KE devices include an enhanced interconnect structure for faster
routing of input signals with high fan-out. Column I/O pins can drive the
FastRow interconnect, which routes signals directly into the local
interconnect without having to drive through the MegaLAB interconnect.
FastRow lines traverse two MegaLAB structures. Also, these pins can
drive the local interconnect directly for fast setup times. On EP20K300E
and larger devices, the FastRow interconnect drives the two MegaLABs in
the top left corner, the two MegaLABs in the top right corner, the two
MegaLABS in the bottom left corner, and the two MegaLABs in the
bottom right corner. On EP20K200E and smaller devices, FastRow
interconnect drives the two MegaLABs on the top and the two MegaLABs
on the bottom of the device. On all devices, the FastRow interconnect
drives all local interconnect in the appropriate MegaLABs except the local
interconnect on the side of the MegaLAB opposite the ESB. Pins using the
FastRow interconnect achieve a faster set-up time, as the signal does not
need to use a MegaLAB interconnect line to reach the destination LE.
Figure 12 shows the FastRow interconnect.
Row Interconnect
MegaLAB Interconnect
LE
Column
Interconnect
Local
Interconnect
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