參數(shù)資料
型號: EP20K400EFC672-3N
廠商: Altera
文件頁數(shù): 38/117頁
文件大?。?/td> 0K
描述: IC APEX 20KE FPGA 400K 672-FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 40
系列: APEX-20K®
LAB/CLB數(shù): 1664
邏輯元件/單元數(shù): 16640
RAM 位總計(jì): 212992
輸入/輸出數(shù): 488
門數(shù): 1052000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 672-BBGA
供應(yīng)商設(shè)備封裝: 672-BGA(27x27)
Altera Corporation
27
APEX 20K Programmable Logic Device Family Data Sheet
Figure 14. APEX 20K Macrocell
For registered functions, each macrocell register can be programmed
individually to implement D, T, JK, or SR operation with programmable
clock control. The register can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired register type; the
Quartus II software then selects the most efficient register operation for
each registered function to optimize resource utilization. The Quartus II
software or other synthesis tools can also select the most efficient register
operation automatically when synthesizing HDL designs.
Each programmable register can be clocked by one of two ESB-wide
clocks. The ESB-wide clocks can be generated from device dedicated clock
pins, global signals, or local interconnect. Each clock also has an
associated clock enable, generated from the local interconnect. The clock
and clock enable signals are related for a particular ESB; any macrocell
using a clock also uses the associated clock enable.
If both the rising and falling edges of a clock are used in an ESB, both
ESB-wide clock signals are used.
Clock/
Enable
Select
Product-
Term
Select
Matrix
Parallel Logic
Expanders
(From Other
Macrocells)
ESB-Wide
Clears
ESB-Wide
Clock Enables
ESB-Wide
Clocks
32 Signals
from Local
Interconnect
Clear
Select
ESB
Output
Programmable
Register
222
ENA
D
CLRN
Q
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