Notes to Table 15: (1) The PLL input frequency range for the EP20K10" />
參數(shù)資料
型號： EP20K400EFC672-3N
廠商： Altera
文件頁數(shù)： 65/117頁
文件大?。?/td> 0K
描述： IC APEX 20KE FPGA 400K 672-FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 40
系列： APEX-20K®
LAB/CLB數(shù)： 1664
邏輯元件/單元數(shù)： 16640
RAM 位總計： 212992
輸入/輸出數(shù)： 488
門數(shù)： 1052000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 672-BBGA
供應(yīng)商設(shè)備封裝： 672-BGA（27x27）
Altera Corporation
51
APEX 20K Programmable Logic Device Family Data Sheet
Notes to Table 15:
(1)
The PLL input frequency range for the EP20K100-1X device for 1x multiplication is 25 MHz to 175 MHz.
(2)
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is
supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock
time is less than the configuration time.
(4)
The jitter specification is measured under long-term observation.
(5)
If the input clock stability is 100 ps, tJITTER is 250 ps.
Table 16 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
tSKEW
Skew delay between related
ClockLock/ClockBoost-generated clocks
500
ps
tJITTER
Jitter on ClockLock/ClockBoost-generated clock
200
ps
tINCLKSTB
Input clock stability (measured between adjacent
clocks)
50
ps
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade Devices
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
170
MHz
fCLK1
Input clock frequency (ClockBoost clock multiplication
factor equals 1)
25
170
MHz
fCLK2
Input clock frequency (ClockBoost clock multiplication
factor equals 2)
16
80
MHz
fCLK4
Input clock frequency (ClockBoost clock multiplication
factor equals 4)
10
34
MHz
tOUTDUTY
Duty cycle for ClockLock/ClockBoost-generated clock
40
60
%
fCLKDEV
Input deviation from user specification in the Quartus II
software (ClockBoost clock multiplication factor equals
one) (1)
25,000 (2)
PPM
tR
Input rise time
5ns
tF
Input fall time
5ns
tLOCK
Time required for ClockLock/ ClockBoost to acquire
lock (3)
10
s
tSKEW
Skew delay between related ClockLock/ ClockBoost-
generated clock
500
ps
tJITTER
Jitter on ClockLock/ ClockBoost-generated clock (4)
200
ps
tINCLKSTB
Input clock stability (measured between adjacent
clocks)
50
ps
相關(guān)PDF資料
PDF描述
EP20K400EFC672-3 IC APEX 20KE FPGA 400K 672-FBGA
IDT70V25L20PFI IC SRAM 128KBIT 20NS 100TQFP
ACM44DRAN CONN EDGECARD 88POS .156 R/A
A54SX16P-PQ208M IC FPGA SX 24K GATES 208-PQFP
A54SX16P-PQG208M IC FPGA SX 24K GATES 208-PQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP20K400EFI672-1ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K400EFI672-2ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
EP20K400EFI672-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400EFI672-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 CPLD - APEX 20K 1664 Macros 488 IO RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP20K400EFI672-3ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FPGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*