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型號(hào)：	EP2S30F672I4
廠商：	Altera
文件頁(yè)數(shù)：	524/768頁(yè)
文件大?。?/td>	0K
描述：	IC STRATIX II FPGA 30K 672-FBGA
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	10
系列：	Stratix® II
LAB/CLB數(shù)：	1694
邏輯元件/單元數(shù)：	33880
RAM 位總計(jì)：	1369728
輸入/輸出數(shù)：	500
電源電壓：	1.15 V ~ 1.25 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	672-BBGA
供應(yīng)商設(shè)備封裝：	672-BGA（27x27）
其它名稱：	544-1899 EP2S30F672I4-ND

Altera Corporation

Stratix II Device Handbook, Volume 2

January 2008

Fast Passive Parallel Configuration

entered user mode. When initialization is complete, the device enters user

mode. In user-mode, the user I/O pins no longer have weak pull-up

resistors and function as assigned in your design.

To ensure DCLK and DATA[7..0] are not left floating at the end of

configuration, the MAX II device must drive them either high or low,

whichever is convenient on your board. The DATA[7..0] pins are

available as user I/O pins after configuration. When you select the FPP

scheme in the Quartus II software, as a default, these I/O pins are

tri-stated in user mode. To change this default option in the Quartus II

software, select the Pins tab of the Device & Pin Options dialog box.

The configuration clock (DCLK) speed must be below the specified

frequency to ensure correct configuration. No maximum DCLK period

exists, which means you can pause configuration by halting DCLK for an

indefinite amount of time.

If you are using the Stratix II or Stratix II GX decompression

and/or design security feature and need to stop DCLK, it can

only be stopped three clock cycles after the last data byte was

latched into the Stratix II or Stratix II GX device.

By stopping DCLK, the configuration circuit allows enough clock cycles to

process the last byte of latched configuration data. When the clock

restarts, the MAX II device must provide data on the DATA[7..0] pins

prior to sending the first DCLK rising edge.

If an error occurs during configuration, the device drives its nSTATUS pin

low, resetting itself internally. The low signal on the nSTATUS pin also

alerts the MAX II device that there is an error. If the Auto-restart

configuration after error

option (available in the Quartus II software

from the General tab of the Device & Pin Options (dialog box) is turned

on, the device releases nSTATUS after a reset time-out period (maximum

of 100 s). After nSTATUS is released and pulled high by a pull-up

resistor, the MAX II device can try to reconfigure the target device

without needing to pulse nCONFIG low. If this option is turned off, the

MAX II device must generate a low-to-high transition (with a low pulse

of at least 2 s) on nCONFIG to restart the configuration process.

The MAX II device can also monitor the CONF_DONE and INIT_DONE

pins to ensure successful configuration. The CONF_DONE pin must be

monitored by the MAX II device to detect errors and determine when

programming completes. If all configuration data is sent, but the

or INIT_DONE signals have not gone high, the MAX II

device will reconfigure the target device.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
EP2S30F672I4N	功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPGA - Stratix II 1694 LABs 500 IOs RoHS:否制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP2S-3G1	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE
EP2S-3G1T	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE
EP2S-3G1TT	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE
EP2S-3G2	制造商:NEC 制造商全稱:NEC 功能描述:LOW SOUND PRESSURE

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