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參數(shù)資料
| 型號： | EP4S100G4F45I3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 19/22頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX IV FPGA 360K 1932FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | STRATIX® IV GT |
| LAB/CLB數(shù)： | 14144 |
| 邏輯元件/單元數(shù)： | 353600 |
| RAM 位總計： | 23105536 |
| 輸入/輸出數(shù)： | 781 |
| 電源電壓： | 0.92 V ~ 0.98 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1932-BBGA |
| 供應商設備封裝： | 1932-FBGA（45x45） |
1–6
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
September 2012
Altera Corporation
Architecture Features
The Stratix IV device family features are divided into high-speed transceiver features
and FPGA fabric and I/O features.
1 The high-speed transceiver features apply only to Stratix IV GX and Stratix IV GT
devices.
High-Speed Transceiver Features
The following sections describe high-speed transceiver features for Stratix IV GX and
GT devices.
Highest Aggregate Data Bandwidth
Up to 48 full-duplex transceiver channels supporting data rates up to 8.5 Gbps in
Stratix IV GX devices and up to 11.3 Gbps in Stratix IV GT devices.
Wide Range of Protocol Support
Physical layer support for the following serial protocols:
■
Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH,
XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON,
SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken
■
Stratix IV GT—40G/100G Ethernet, SFI-S, Interlaken, SFI-5.1, Serial RapidIO,
SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, 3G-SDI, and Fibre Channel
■
Extremely flexible and easy-to-configure transceiver data path to implement
proprietary protocols
■
PCIe Support
■
Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCI
Express base specification 2.0 that includes PHY-MAC, Data Link, and
transaction layer circuitry embedded in PCI Express hard IP blocks
f For more information, refer to the PCI Express Compiler User Guide.
■
Root complex and end-point applications
■
x1, x4, and x8 lane configurations
■
PIPE 2.0-compliant interface
■
Embedded circuitry to switch between Gen1 and Gen2 data rates
■
Built-in circuitry for electrical idle generation and detection, receiver detect,
power state transitions, lane reversal, and polarity inversion
■
8B/10B encoder and decoder, receiver synchronization state machine, and
± 300 parts per million (ppm) clock compensation circuitry
■
Transaction layer support for up to two virtual channels (VCs)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP4S100G5F45I1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G5F45I1N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G5F45I1NGA | 制造商:Altera Corporation 功能描述: |
| EP4S100G5F45I2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP4S100G5F45I2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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