參數(shù)資料
型號： EP4S100G4F45I3N
廠商： Altera
文件頁數(shù)： 21/22頁
文件大?。?/td> 0K
描述： IC STRATIX IV FPGA 360K 1932FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 3
系列： STRATIX® IV GT
LAB/CLB數(shù)： 14144
邏輯元件/單元數(shù)： 353600
RAM 位總計： 23105536
輸入/輸出數(shù)： 781
電源電壓： 0.92 V ~ 0.98 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 1932-BBGA
供應(yīng)商設(shè)備封裝： 1932-FBGA（45x45）
1–8
Chapter 1: Overview for the Stratix IV Device Family
Architecture Features
September 2012
Altera Corporation
FPGA Fabric and I/O Features
The following sections describe the Stratix IV FPGA fabric and I/O features.
Device Core Features
■
Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in
Stratix IV E devices, efficiently packed in unique and innovative adaptive logic
modules (ALMs)
■
Ten ALMs per logic array block (LAB) deliver faster performance, improved logic
utilization, and optimized routing
■
Programmable power technology, including a variety of process, circuit, and
architecture optimizations and innovations
■
Programmable power technology available to select power-driven compilation
options for reduced static power consumption
Embedded Memory
■
TriMatrix embedded memory architecture provides three different memory block
sizes to efficiently address the needs of diversified FPGA designs:
■
640-bit MLAB
■
9-Kb M9K
■
144-Kb M144K
■
Up to 33,294 Kb of embedded memory operating at up to 600 MHz
■
Each memory block is independently configurable to be a single- or dual-port
RAM, FIFO, ROM, or shift register
Digital Signal Processing (DSP) Blocks
■
Flexible DSP blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit
full-precision multipliers at up to 600 MHz with rounding and saturation
capabilities
■
Faster operation due to fully pipelined architecture and built-in addition,
subtraction, and accumulation units to combine multiplication results
■
Optimally designed to support advanced features such as adaptive filtering, barrel
shifters, and finite and infinite impulse response (FIR and IIR) filters
Clock Networks
■
Up to 16 global clocks and 88 regional clocks optimally routed to meet the
maximum performance of 800 MHz
■
Up to 112 and 132 periphery clocks in Stratix IV GX and Stratix IV E devices,
respectively
■
Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in
Stratix IV GX and Stratix IV GT devices
■
Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in
Stratix IV E devices
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP4S100G5F45I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4S100G5F45I1N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4S100G5F45I1NGA 制造商:Altera Corporation 功能描述:
EP4S100G5F45I2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EP4S100G5F45I2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix IV 21248 LABs 781 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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