Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) DS508F2 EP7312 High-Performance, Low-Power S" />
參數(shù)資料
型號: EP7312-CB
廠商: Cirrus Logic Inc
文件頁數(shù): 37/54頁
文件大?。?/td> 0K
描述: IC ARM720T MCU 74MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: EP7
核心處理器: ARM7
芯體尺寸: 32-位
速度: 74MHz
連通性: 編解碼器,DAI,EBI/EMI,IrDA,鍵盤,SPI/Microwire1,UART/USART
外圍設(shè)備: LCD,LED,MaverickKey,PWM
輸入/輸出數(shù): 27
程序存儲器類型: ROMless
RAM 容量: 56K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 2.7 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-BGA
包裝: 托盤
配用: 598-1209-ND - KIT DEVELOPMENT EP73XX ARM7
其它名稱: 598-1232
42
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
DS508F2
EP7312
High-Performance, Low-Power System on Chip
F13
nBATCHG
I
Battery changed sense input
F14
VSSIO
Pad ground
I/O ground
F15
D[11]
1
Low
I/O
Data I/O
F16
VDDIO
Pad power
Digital I/O power, 3.3V
G1
PB[1]
1
Input
IGPIO port B
G2
VDDIO
Pad power
Digital I/O power, 3.3V
G3
TDO
1
Input
O
JTAG data out
G4
PB[4]
1
Input
IGPIO port B
G5
PB[6]
1
Input
IGPIO port B
G6
VSSCore
Core ground
G7
VSSRTC
RTC ground
Real time clock ground
G8
DD[0]
1
Low
O
LCD serial display data
G9
D[3]
1
Low
I/O
Data I/O
G10
VSSRTC
RTC ground
Real time clock ground
G11
A[7]
1
Low
O
System byte address
G12
A[8]
1
Low
O
System byte address
G13
A[9]
1
Low
O
System byte address
G14
VSSIO
Pad ground
I/O ground
G15
D[12]
1
Low
I/O
Data I/O
G16
D[13]
1
Low
I/O
Data I/O
H1
PA[7]
1
Input
I/O
GPIO port A
H2
PA[5]
1
Input
I/O
GPIO port A
H3
VSSIO
Pad ground
I/O ground
H4
PA[4]
1
Input
I/O
GPIO port A
H5
PA[6]
1
Input
I/O
GPIO port A
H6
PB[0]
1
Input
I/O
GPIO port B
H7
PB[2]
1
Input
I/O
GPIO port B
H8
VSSRTC
RTC ground
Real time clock ground
H9
VSSRTC
RTC ground
Real time clock ground
H10
A[10]
1
Low
O
System byte address
H11
A[11]
1
Low
O
System byte address
H12
A[12]
1
Low
O
System byte address
H13
A[13]/DRA[14]
1
Low
O
System byte address / SDRAM address
H14
VSSIO
Pad ground
I/O ground
H15
D[14]
1
Low
I/O
Data I/O
H16
D[15]
1
Low
I/O
Data I/O
J1
PA[3]
1
Input
I/O
GPIO port A
J2
PA[1]
1
Input
I/O
GPIO port A
J3
VSSIO
Pad ground
I/O ground
J4
PA[2]
1
Input
I/O
GPIO port A
J5
PA[0]
1
Input
I/O
GPIO port A
J6
TXD[1]
1
High
O
UART 1 transmit data out
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Strength
Reset
State
Type
Description
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