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參數(shù)資料
| 型號： | EP9315-CB |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM920T MCU 200MHZ 352-PBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | EP9 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 200MHz |
| 連通性： | EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB |
| 外圍設(shè)備： | AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 352-BGA |
| 包裝： | 托盤 |
| 配用： | 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9 |
| 其它名稱： | 598-1261 |
ER638E2B
3
HDLC
Description
When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified
by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of
the packet to memory, so that the last one to fifteen bytes of a packet may not be accessible.
Workaround
To ensure that the DMA channel empties the buffer, do the following (in the HDLC interrupt handler, for
example):
1) Note the values in the MAXCNTx and REMAIN registers for the DMA channel. The difference is the num-
ber of bytes read from the UART/HDLC, which is the size of the HDLC packet. Call this number N. Note
that the BC field of the UART1HDLCRXInfoBuf register should also be N.
2) Temporarily disable the UART DMA RX interface by clearing the RXDMAE bit in the UART1DMACtrl reg-
ister.
3) Wait until the difference between the CURRENTx and BASEx registers in the DMA channel is equal to
N + 1.
At this point, the rest of the packet is guaranteed to have been written to memory. Using this method will
cause an extra byte to be read from the UART by the DMA channel and also written to memory. This last
byte should be ignored.
SDRAM Controller
Description 1
Using the SDRAM controller in auto-precharge mode will produce system instability at external bus speeds
greater than 50MHz.
Workaround
Do not turn on the auto-precharge feature of the SDRAM controller if the external bus speed will be greater
than 50 MHz.
Description 2
When the SDRAM controller is configured for PRECHARGE ALL command, the actual sequence is not
always issued to the SDRAM device(s).
Workaround
Do a read from each SDRAM bank so that a PRECHARGE command is issued to each bank of the SDRAM
device. This will satisfy the required SDRAM initialization sequence.
Due to the effectiveness and simplicity of the software workaround, no silicon fix is planned.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP9315CB/E0 | 制造商:Cirrus Logic 功能描述: |
| EP9315CB/E1 | 制造商:Cirrus Logic 功能描述: |
| EP9315-CBZ | 功能描述:微處理器 - MPU IC Universl Pltform ARM9 SOC Prcessor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| EP9315-EB | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Enhanced Universal Platform System-on-Chip Processor |
| EP9315-EBZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Enhanced Universal Platform System-on-Chip Processor |
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