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參數(shù)資料
| 型號： | EP9315-CB |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM920T MCU 200MHZ 352-PBGA |
| 標準包裝： | 40 |
| 系列： | EP9 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 200MHz |
| 連通性： | EBI/EMI，EIDE，以太網(wǎng)，I²C，IrDA，鍵盤/觸摸屏，PCMCIA，SPI，UART/USART，USB |
| 外圍設備： | AC'97，DMA，I²S，LCD，LED，MaverickKey，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 16 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 352-BGA |
| 包裝： | 托盤 |
| 配用： | 598-1144-ND - KIT DEVELOPMENT EP9315 ARM9 |
| 其它名稱： | 598-1261 |
8
ER638E2B
Workaround
The simplest workaround is to insure that no two such instructions ever appear in the instruction stream
consecutively. Specifically, a conditional coprocessor instruction should not precede a load/store 64/double.
Simply inserting another ARM or coprocessor instruction accomplishes this:
cfaddne
c0, c1, c2
; assume this does not execute
nop
; inserted extra instruction here
cfldrd
c3, [r2, #0x0]
Cases where branches may be taken also needs to be handled. In this particular case, the first instruction
is moved earlier in the instruction stream by exchanging it with the previous one:
target
cfldrd
c3, [r2, #0x0]
b
target
cfadd
c0, c1, c2
; though in pipeline, this does not execute
nop
To avoid this error when entering exception and interrupt handlers, the first instruction in an interrupt or
exception handler should not be a coprocessor instruction. Since the first instruction is normally a branch,
this error should not appear.
Description 2
Under certain circumstances, incorrect values may be used for arithmetic calculations or stored in memory.
The error appears as follows.
1) Execute a coprocessor instruction whose target is one of the coprocessor general purpose register c0
through c15.
2) Let the second instruction be an instruction with the same target, but not be executed1.
3) Execute a third instruction at least one of whose operands is the target of the previous two instructions.
For example, assume no pipeline interlocks other than the dependencies involving register c0 in the
following instruction sequence:
cfadd32
c0, c1, c2
cfsub32ne
c0, c3, c4
; assume this does not execute
cfstr32
c0, [r2, #0x0]
In this particular case, the incorrect value stored at the address in r2 is the previous value in c0, not the
expected one resulting from the cfadd32.
(Continued)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EP9315CB/E0 | 制造商:Cirrus Logic 功能描述: |
| EP9315CB/E1 | 制造商:Cirrus Logic 功能描述: |
| EP9315-CBZ | 功能描述:微處理器 - MPU IC Universl Pltform ARM9 SOC Prcessor RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| EP9315-EB | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Enhanced Universal Platform System-on-Chip Processor |
| EP9315-EBZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Enhanced Universal Platform System-on-Chip Processor |
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