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參數資料
| 型號： | EPC1PI8N |
| 廠商： | Altera |
| 文件頁數： | 16/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 1MBIT 8-DIP |
| 產品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 100 |
| 系列： | EPC |
| 可編程類型： | OTP |
| 存儲容量： | 1Mb |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 產品目錄頁面： | 604 (CN2011-ZH PDF) |
| 配用： | PLMJ1213-ND - PROGRAMMER ADAPTER 20 PIN J-LEAD |
| 其它名稱： | 544-1375-5 EPC1PI8N-ND |
Pin Information
Page 23
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
TCK
N/A
3
32
Input
JTAG clock pin. Connect this pin to GND if the JTAG
circuitry is not used.
This pin is only available in EPC2 devices.
VCCSEL
N/A
5
3
Input
Mode select for VCC supply. VCCSEL must be connected to
GND if the device uses a 5.0-V power supply (VCC = 5.0 V).
VCCSEL
must be connected to VCC if the device uses a
3.3-V power supply (VCC = 3.3 V).
This pin is only available in EPC2 devices.
VPPSEL
N/A
14
17
Input
Mode select for V
PP. supply. VPPSEL must be connected to
GND if VPP uses a 5.0-V power supply (VPP = 5.0 V).
VPPSEL
must be connected to VCC if VPP uses a 3.3-V
power supply (VPP = 3.3 V).
This pin is only available in EPC2 devices.
VPP
N/A
18
23
Power
Programming power pin. For the EPC2 device, this pin is
normally tied to VCC. If the VCC of the EPC2 device is 3.3 V,
tie VPP to 5.0 V to improve ISP time. For EPC1 and
EPC1441 devices, VPP must be tied to VCC.
This pin is only available in EPC2 devices.
VCC
7, 8
20
27
Power
Power pin.
GND
5
10
12
Ground
Ground pin. Place a 0.2-F decoupling capacitor between
the VCC and GND pins.
Notes to Table 20:
(1) This package is available for EPC1 and EPC1441 devices only.
(2) This package is available for EPC2 and EPC1441 devices only.
Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 3 of 3)
Pin Name
Pin Number
Pin Type
Description
8-Pin
PDIP (1)
20-Pin
PLCC
32-Pin
TQFP (2)
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