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參數(shù)資料
| 型號(hào)： | EPC1PI8N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 23/26頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CONFIG DEVICE 1MBIT 8-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | EPC |
| 可編程類型： | OTP |
| 存儲(chǔ)容量： | 1Mb |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 604 (CN2011-ZH PDF) |
| 配用： | PLMJ1213-ND - PROGRAMMER ADAPTER 20 PIN J-LEAD |
| 其它名稱： | 544-1375-5 EPC1PI8N-ND |
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Page 6
Device Configuration
Configuration Devices for SRAM-Based LUT Devices
January 2012
Altera Corporation
Device Configuration
The EPC1, EPC2, and EPC1441 devices store configuration data in its erasable
programmable read-only memory (EPROM) array and serially clock data out using
an internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the
address counter and the DATA output tri-state buffer. The configuration device sends a
serial bitstream of configuration data to its DATA pin, which is routed to the DATA0
input of the FPGA.
The control signals for configuration devices, OE, nCS, and DCLK, interface directly with
the FPGA control signals, nSTATUS, CONF_DONE, and DCLK. All Altera FPGAs can be
configured by a configuration device without requiring an external intelligent
controller.
1 An EPC2 device cannot configure FLEX 8000 or FLEX 6000 devices. For configuration
devices that support FLEX 8000 or FLEX 6000 devices, refer to Table 2.
Figure 2 shows the basic configuration interface connections between the
configuration device and the Altera FPGA.
The EPC2 device allows you to begin configuration of the FPGA using an additional
pin, nINIT_CONF. The nINIT_CONF pin of the EPC2 device can be connected to the
nCONFIG
pin of the FPGA, which allows the INIT_CONF JTAG instruction to begin
FPGA configuration. The INIT_CONF JTAG instruction causes the EPC2 device to drive
the nINIT_CONF pin low, which in turn pulls the nCONFIG pin low. Pulling the nCONFIG
pin low on the FPGA will reset the device. When the JTAG state machine exits this
state, the nINIT_CONF pin is released and pulled high by an internal 1-k resistor,
which in turn pulls the nCONFIG pin high to begin configuration. If you do not use the
nINIT
_CONF pin, disconnect the nINIT_CONF pin, and pull the nCONFIG pin of the FPGA
to VCC either directly or through a resistor.
Figure 2. Altera FPGA Configured Using an EPC1, EPC2, or EPC1441 Configuration Device (1)
Notes to Figure 2:
(1) For more information about configuration interface connections, refer to the configuration chapter in the appropriate device handbook.
(2) The nINIT_CONF pin which is available on EPC2 devices has an internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the nINIT_CONF/nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used.
If the nINIT_CONF pin is not used or unavailable, nCONFIG must be pulled to VCC either directly or through a resistor.
(3) EPC2 devices have internal programmable pull-up resistors on OE and nCS pins. If internal pull-up resistors are used, do not use external pull-up
resistors on these pins. The internal pull-up resistors are set by default in the Quartus II software. To turn off the internal pull-up resistors, check
the Disable nCS and OE pull-ups on configuration device option when you generate programming files.
FPGA
Configuration
Device
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
MSEL
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
VCC
GND
nCE
VCC
nCEO
nCASC
N.C.
n
(2)
(3)
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