參數(shù)資料
型號: EPM9560ARI208-10
廠商: Altera
文件頁數(shù): 10/46頁
文件大?。?/td> 0K
描述: IC MAX 9000 CPLD 560 208-RQFP
產(chǎn)品變化通告: Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝: 48
系列: Max® 9000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目: 35
宏單元數(shù): 560
門數(shù): 12000
輸入/輸出數(shù): 153
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-RQFP(28x28)
包裝: 托盤
其它名稱: 544-2364
18
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
The output buffer in each IOC has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces board-level noise and adds a nominal timing delay to the
output buffer delay (tOD) parameter. The fast slew rate should be used for
speed-critical outputs in systems that are adequately protected against
noise. Designers can specify the slew rate on a pin-by-pin basis during
design entry or assign a default slew rate to all pins on a global basis. The
slew rate control affects both rising and falling edges of the output signals.
Output
Configuration
The MAX 9000 device architecture supports the MultiVolt I/O interface
feature, which allows MAX 9000 devices to interface with systems of
differing supply voltages. The 5.0-V devices in all packages can be set for
3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins
for internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply.
With a 5.0-V VCCINT level, input voltages are at TTL levels and are
therefore compatible with 3.3-V and 5.0-V inputs.
Table 6. Peripheral Bus Sources
Peripheral Control
Signal
Source
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
OE0/ENA0
Row C
Row E
Row F
Row G
OE1/ENA1
Row B
Row E
Row F
OE2/ENA2
Row ARow ERow ERow E
OE3/ENA3
Row BRow BRow BRow B
OE4/ENA4
Row ARow ARow ARow A
OE5
Row DRow DRow DRow D
OE6
Row CRow CRow CRow C
OE7/CLR1
Row B/GOE
CLR0/ENA5
Row A/GCLR
CLK0
GCLK1
CLK1
GCLK2
CLK2
Row DRow DRow DRow D
CLK3
Row CRow CRow CRow C
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