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參數(shù)資料
| 型號： | EPM9560ARI208-10 |
| 廠商： | Altera |
| 文件頁數(shù)： | 46/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MAX 9000 CPLD 560 208-RQFP |
| 產(chǎn)品變化通告： | Package Change 30/Jun/2010 |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | Max® 9000 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 邏輯元件/邏輯塊數(shù)目： | 35 |
| 宏單元數(shù)： | 560 |
| 門數(shù)： | 12000 |
| 輸入/輸出數(shù)： | 153 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 208-RQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | 544-2364 |
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Altera Corporation
9
MAX 9000 Programmable Logic Device Family Data Sheet
For registered functions, each macrocell register can be individually
programmed for D, T, JK, or SR operation with programmable clock
control. The flipflop can also be bypassed for combinatorial operation.
During design entry, the user specifies the desired register type; the
MAX+PLUS II software then selects the most efficient register operation
for each registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
■
By either global clock signal. This mode achieves the fastest clock-to-
output performance.
■
By a global clock signal and enabled by an active-high clock enable.
This mode provides an enable on each flipflop while still achieving
the fast clock-to-output performance of the global clock.
■
By an array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available. As shown in Figure 2, these global
clock signals can be the true or the complement of either of the global clock
pins (DIN1 and DIN2).
Each register also supports asynchronous preset and clear functions. As
shown in Figure 3, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear inputs to registers are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the dedicated global clear pin
(DIN3). The global clear can be programmed for active-high or active-low
operation.
All MAX 9000 macrocells offer a dual-output structure that provides
independent register and combinatorial logic output within the same
macrocell. This function is implemented by a process called register
packing. When register packing is used, the product-term select matrix
allocates one product term to the D input of the register, while the
remaining product terms can be used to implement unrelated
combinatorial logic. Both the registered and the combinatorial output of
the macrocell can feed either the FastTrack Interconnect or the LAB local
array.
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參數(shù)描述 |
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| EPM9560ARI24010 | 制造商:Altera Corporation 功能描述: |
| EPM9560ARI240-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9560BI356-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9560BI356-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9560GI280-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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