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Altera Corporation

MAX 9000 Programmable Logic Device Family Data Sheet

Timing Model

The continuous, high-performance FastTrack Interconnect ensures

predictable performance and accurate simulation and timing analysis.

This predictable performance contrasts with that of FPGAs, which use a

segmented connection scheme and hence have unpredictable

performance. Timing simulation and delay prediction are available with

the MAX+PLUS II Simulator and Timing Analyzer, or with industry-

standard EDA tools. The Simulator offers both pre-synthesis functional

simulation to evaluate logic design accuracy and post-synthesis timing

simulation with 0.1-ns resolution. The Timing Analyzer provides point-

to-point timing delay information, setup and hold time prediction, and

device-wide performance analysis.

The MAX 9000 timing model in Figure 14 shows the delays that

correspond to various paths and functions in the circuit. This model

contains three distinct parts: the macrocell, IOC, and interconnect,

including the row and column FastTrack Interconnect and LAB local array

paths. Each parameter shown in Figure 14 is expressed as a worst-case

value in the internal timing characteristics tables in this data sheet. Hand-

calculations that use the MAX 9000 timing model and these timing

parameters can be used to estimate MAX 9000 device performance.

f For more information on calculating MAX 9000 timing delays, see

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
EPM9560BI356-15	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:
EPM9560BI356-20	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:
EPM9560GI280-15	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:
EPM9560GI280-20	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:
EPM9560RC208-15	制造商:Altera Corporation 功能描述:IC MAX

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