- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16558 > EV-ADF4106SD1Z (Analog Devices Inc)BOARD EVAL FOR ADF4106SD1Z PDF資料下載
參數(shù)資料
| 型號(hào)： | EV-ADF4106SD1Z |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADF4106SD1Z |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
ADF4106
Data Sheet
Rev. E | Page 18 of 24
Charge Pump Currents
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table 9.
Prescaler Value
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 325 MHz. Therefore,
with an RF frequency of 4 GHz, a prescaler value of 16/17 is
valid, but a value of 8/9 is not valid.
PD Polarity
This bit sets the phase detector polarity bit. See Table 9.
CP Three-State
This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.
THE INITIALIZATION LATCH
When C2 and C1 = 1 and 1, respectively, the initialization latch
is programmed. This is essentially the same as the function
latch (programmed when C2 and C1 = 1 and 0, respectively).
However, when the initialization latch is programmed, there is
an additional internal reset pulse applied to the R and N (A, B)
counters. This pulse ensures that the N (A, B) counter is at the
load point when the N (A, B) counter data is latched and the
device begins counting in close phase alignment.
If the latch is programmed for synchronous power-down (CE
pin is high, PD1 bit is high, and PD2 bit is low), the internal
pulse also triggers this power-down. The prescaler reference
and the oscillator input buffer are unaffected by the internal
reset pulse; therefore, close phase alignment is maintained when
counting resumes.
When the first N (A, B) counter data is latched after
initialization, the internal reset pulse is again activated.
However, successive N (A, B) counter loads after this will not
trigger the internal reset pulse.
Device Programming After Initial Power-Up
After initial power up of the device, there are three methods for
programming the device: initialization latch, CE pin, and
counter reset.
Initialization Latch Method
Apply VDD.
Program the initialization latch (11 in two LSBs of input
word). Make sure that the F1 bit is programmed to 0.
Do a function latch load (10 in two LSBs of the control
word), making sure that the F1 bit is programmed to a 0.
Do an R load (00 in two LSBs).
Do an N (A, B) load (01 in two LSBs).
When the initialization latch is loaded, the following occurs:
The function latch contents are loaded.
An internal pulse resets the R, N (A, B), and timeout counters
to load-state conditions and also three-states the charge
pump. Note that the prescaler band gap reference and the
oscillator input buffer are unaffected by the internal reset
pulse, allowing close phase alignment when counting
resumes.
Latching the first N (A, B) counter data after the initialization
word activates the same internal reset pulse. Successive N (A,
B) loads will not trigger the internal reset pulse, unless there
is another initialization.
CE PIN METHOD
Apply VDD.
Bring CE low to put the device into power-down. This is an
asychronous power-down in that it happens immediately.
Program the function latch (10).
Program the R counter latch (00).
Program the N (A, B) counter latch (01).
Bring CE high to take the device out of power-down. The R
and N (A, B) counters now resume counting in close
alignment.
Note that after CE goes high, a 1 s duration may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
CE can be used to power the device up and down to check for
channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled as
long as it is programmed at least once after VDD is initially
applied.
COUNTER RESET METHOD
Apply VDD.
Do a function latch load (10 in two LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
Do an R counter load (00 in two LSBs).
Do an N (A, B) counter load (01 in two LSBs).
Do a function latch load (10 in two LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the
initialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump but does not trigger
synchronous power-down.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EBC36DRTS-S13 | CONN EDGECARD 72POS .100 EXTEND |
| HBM12DRKH | CONN EDGECARD 24POS DIP .156 SLD |
| V48C24T75BF3 | CONVERTER MOD DC/DC 24V 75W |
| TCM809MVNB713 | IC RESET MONITOR 4.38V SOT23B-3 |
| EV-ADF4156SD1Z | BOARD EVAL FOR ADF4156 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EV-ADF4108EB1Z | 功能描述:BOARD EVAL FOR ADF4108EB1Z RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EV-ADF4108EB2Z | 功能描述:BOARD EVAL FOR ADF4108EB2Z RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EV-ADF4113HVSD1Z | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Evaluation Board I.C. ADF4113HV RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| EV-ADF411XSD1Z | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Evaluation Board I.C. RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| EV-ADF4153ASD1Z | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Evaluation Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。