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| 型號： | EVAL-AD1937AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1937 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻編解碼器 |
| 已用 IC / 零件： | AD1937 |
| 主要屬性： | 24 位，192 kHz，4 ADC: 107dB 動態(tài)范圍，8 DAC: 112dB 動態(tài)范圍 |
| 次要屬性： | 分時(shí)復(fù)用（TDM）、I2C 和 SPI 接口，Popguard? 技術(shù) |
| 已供物品： | 板 |
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AD1937
Rev. B | Page 19 of 36
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
The ADC and DAC serial data modes default to I2S stereo.
The ports can also be programmed for left-justified stereo,
right-justified stereo, and TDM modes. The word width is
24 bits by default and can be set to 16 or 20 bits in the DAC
Control 2 and ADC Control 1 registers. The DAC serial formats
are programmable in the DAC Control 0 register. The polarity of
DBCLK and DLRCLK is programmable in the DAC Control 1 reg-
ister. The ADC serial format is programmable in ADC Control 1
register. The ABCLK and ALRCLK clock polarities are pro-
Figure 15 all of the clocks are shown with their normal polarity.
Both DAC and ADC serial ports can be programmed to become
the bus masters according to DAC Control 1 and ADC Control 2
registers. By default, both ADC and DAC serial ports are in the
slave mode.
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
MSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDATA
LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB
1/
fS
0
74
14-
02
4
Figure 15. Stereo Modes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1937EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| EVAL-AD1937EBZ | 制造商:Analog Devices 功能描述:EB SINGLE CHIP CODEC 4 ADC'S W/DIFF OUTP - Boxed Product (Development Kits) |
| EVAL-AD1938AZ | 功能描述:BOARD EVAL FOR AD1938 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-AD1938EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC |
| EVAL-AD1938EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR MULTI CHANNEL 96KHZ CODEC - Boxed Product (Development Kits) |
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